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Measure HSIC USB without disturbing the system

Posted: 01 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:high speed inter-chip USB? application processors? wireless modems?

Recently, high speed inter-chip USB (HSIC USB) has become popular for connecting application processors to wireless modems and other peripherals in smartphones, tablets, and other mobile products. The specification adapts high-speed USB 2.0 for chip-to-chip use by changing the PHY layer to reduce power and make the PHY more compatible with standard digital logic processes. However, changing the PHY introduces test and measurement problems. Current USB analyzers don't work because the new PHY is not interoperable with the standard USB 2.0 PHY in standard USB analyzers, and the bus is difficult to measure using standard scopes and probes.

USB 2.0 was designed for upward compatibility with USB 1.1 devices, hosts and cables. The PHY is designed to drive 5m cables, using 3.3V signaling. Three speeds are supported: 1.5Mbit/s, 12Mbit/s and 480Mbit/s. The lower two speeds use differential voltage-mode signaling. The high-speed uses differential current-mode signaling, with a terminated bus. The combination typically requires an analog-compatible process, and a PLL for clock recovery.

HSIC USB has no need for backward compatibility, because it's chip-to-chip. The PHY is designed to drive 10 cm traces on the PC board, using 1.2V signaling. The PHY supports only high-speed USB. The data clock is explicitly signaled (on a signal named STROBE), and data is sent single-ended. DDR techniques allow the STROBE to operate at 240MHz for 480Mbit/s signaling. Legacy speeds (1.5Mbit/s, 12Mbit/s) are not supported. The resulting PHY is easy to implement without using analog cells.

This approach results in a simple, yet flexible interconnect system. Only two pins are needed on the host or device. If the PHY is running at 100% duty cycle, the power consumed for signaling will be only about 9.6 mW; if the PHY is idle, then only leakage currents consume power (in contrast, the typical USB 2.0 PHY consumes 50 mW while active, and tens of mW while idle between transactions.) Best of all, standard USB system software can be used unchanged.

Measurement issues
The HSIC PHY bus can be difficult to measure. To see why, let's examine a typical HSIC USB transaction.

USB data is transferred in units called "transactions." Each HSIC USB transaction begins and ends with the bus in idle. At these times, weak pull-up/pull-down resistors keep STROBE high, and DATA low. When the transaction begins, the outputs of the transmitting PHY are enabled, and the signals are driven with low-impedance LVCMOS drivers. At the end of the transaction, the idle state is actively signaled for two strobe periods; then the transmitting PHY disables the drivers, and the weak pull-up/pull-down resistors passively retain the idle state.

It's critical to bus operation that the idle state be maintained. If an HSIC USB device detects STROBE low and DATA low for two Strobe periods, it treats this as a USB reset condition. This will reset all aspects of the USB device controller, causing communication with the host to be disrupted.

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