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KALRAY completes 256-core SoC using Mentor's sol'ns

Posted: 30 Oct 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Olympus-SoC? Calibre? Tessent? KALRAY? MPPA?

Mentor Graphics Corp. has revealed that KALRAY S.A. has completed its 160 million gate, three billion transistor multipurpose processor array IC. According to the company, it used Mentor Graphics' functional verification, physical design and verification, and design-for-test flow incorporating the Questa, Olympus-SoC, Calibre and Tessent product suites.

The KALRAY MPPA-256 manycore processor is a 256-core SoC with 47MB memory. It is organised as 16 clusters of 16 cores and is implemented using 28nm manufacturing process technology. The cores work in parallel and communicate together via a high-speed low-latency network-on-chip, just as large clusters of computers do in a datacenter. Multiple MPPA chips can be interconnected at the PCB level through Interlaken interfaces to increase the processor array size and performance capability. MPPA manycore processors target the embedded computing market in such sectors as image and signal processing, scientific computing, data security, industrial, aeronautics and transportation.

KALRAY used an OVM-based functional verification methodology using the Mentor Questa product, which provides AXI protocol support in the Questa Verification IP Library. For physical design (layout), they chose the Olympus-SoC place-and-route system for its ability to handle large capacity hierarchical designs with multi-threaded routing and timing analysis, multi-corner multi-mode based multi-voltage flow, and built-in Calibre signoff inside the Olympus-SoC system. The Calibre platform, including Calibre nmDRC, Calibre nmLVS and DFM tools, was used for its large capacity and high performance. KALRAY was able to run DRC in multi-threaded mode with up to 160 CPUs to reduce turnaround time. KALRAY chose the Tessent silicon test platform for memory built-in self-test (BIST) implementation and for high-compression automatic test pattern generation (ATPG) of both stuck-at and high-speed transition fault tests.





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