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Address power, security issues with antifuse tech

Posted: 05 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:digital wallets? non-volatile memory? antifuse?

NVM technology that uses other storage elementseFuse and ROMaddresses the power problem but has its own limitations. The eFuse has limited storage capacity due to its low density. ROM offers great cost, performance, and power capability, but is limited by its design, validation, and manufacturing cycle. Data is stored in the silicon of the ROM array using via or diffusion. ROM contents must be included in the GDSII of the SoC prior to mask making. Once the SoC is fabricated, changing its ROM contents requires a new mask set and full manufacturing cycle, both costly in time and money. Using many ROM versions of the same base design is costly and presents operations challenges (e.g. supply forecasting and inventory management; not having the right product mix at the right time is opportunity lost).

Security vulnerabilities in embedded designs
In the simple design shown in figure 1, the security vulnerabilities are apparent. The stored content of the external EEPROM/Flash are susceptible to non-invasive as well as invasive attacks. A simple attack would be monitoring the flow of data moving between CPU and external memory either with a physical connection or via a clever software hack as described in the New York Times "From Black Hat: Hackers Demonstrate a Rising Vulnerability of Smartphones."4

Embedded as well as external floating gate non-volatile memory technologies are also vulnerable to several low-cost non-invasive information attacks including Glitching and Data Remanence, and semi-invasive approaches including UV attacks, Fault Injection, and Voltage Contrast. For an overview of these techniques, see Dr. Sergei Skorobogatov's presentation "Physical Attacks on Tamper Resistance: Progress and Lessons,"5 which details how easy it is to access stored content in floating gate memory.

Embedded non-volatile memory based on blown fuse links (eFuse) or hard-wired memory (ROM) is immune from non-invasive attacks. However these storage mechanisms relinquish their contents easily through semi-invasive methods such as device de-processing and observation of the silicide or metal link break through a focused ion beam (FIB) microscope.

Integrated memory system
For designs that require the lowest power with high security, a better memory system architecture is required. One element of such architecture is integrating external EEPROM/Flash NVM on chip, immediately lowering power consumption, boosting security, and reducing the system bill of materials by one component.

However, integrating external EEPROM/Flash breaks down at 65nm and below, where the floating gate structures used to create EEPROM and Flash becomes a challenge for technical and business reasons. Floating gate technologies may migrate down process geometries, but for today's development, floating gate is a non-starter in 65nm and below.

The antifuse solution
NVM technology by its nature consumes no power when memory is not being accessed and all embedded NVM solutions discussed meet the low power mandated by mobile monitoring devices and digital wallet chips. However, of the available embedded NVMs, antifuse technology offers the best combination of power, security, and programming flexibility. The table shows some typical characteristics of a mobile SoC.

Table: Typical design requirements for ultra low-power SoCs.

Power and security advantages of an antifuse OTP are derived from the way data is stored in its fundamental storage bit cell. For example, one of Kilopass' developed antifuse bit cells consists of two NMOS transistors: one for programming and a second select transistor that is coupled in series. Applying a voltage to the programming transistor produces a breakdown in its gate dielectric. The breakdown creates a connection between the gate and the channel of the transistor. Thus, a high resistance gate dielectric becomes a low resistance silicon link: changing the cell state from a zero "0" to a one "1".

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