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Cadence designs test chip for 14nm SOI FinFET

Posted: 06 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:processor test chip? silicon-on-insulator FinFET? SoC?

As part of its multi-year partnership with ARM and IBM, Cadence Design Systems announced that it has designed a processor test chip to be implemented in a 14nm silicon-on-insulator FinFET manufacturing process. The chip will primarily check design parameters and intellectual property.

Besides the ARM core, the design includes SRAM and other circuit blocks. Measurements of the test-chip can provide characterisation data necessary for the development of FinFET-based physical IP by ARM, Cadence said. The design includes support for double patterning of lithography.

"The tape-out of this 14nm test chip is the culmination of the significant progress we have made with FinFET on SOI utilising it's built-in dielectric isolation," said Gary Patton, vice president of IBM Semiconductor Research and Development Center, in a statement issued by Cadence.

The chip was designed with Cadence's Encounter digital design tools using FinFET standard cell libraries designed with Cadence's Virtuoso tools.

- Peter Clarke
??EE Times





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