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Aldec ready to tackle Platform Validation topics

Posted: 09 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Platform Validation? HES-7 boards? embedded system? Universal Verification Methodology? Direct Programming Interface?

A paper on Platform Validation at Verification Futures 2012 will be presented by Aldec Inc. One of the EDA industry's hottest topics, Platform Validation is currently at the centre of SoC hardware and software co-verification.

Technology trends, such as embedded processors and time-to-market demands have created a mandate that software engineers have early access to silicon. Platform Validation extends beyond the realms of hardware design simulation and functional verification (which Aldect is known for) and pushes into system hardware and software co-verification.

Jacek Majkowski, Senior Hardware Engineer with Aldec comments,?"Whilst embedded system complexity is growing very fast, driven by high customer expectations, verification tools need to keep pace by providing hardware-based methodologies for SoC designers. The complexity grows in both setup of the design under test and the runtime stage of the test. With Aldec's new HES-7 platform, setup of the high capacity designs is far simpler with the ability to scale the available capacity of the tool, while Standard Co-Emulation Modelling Interface (SCE-MI) interface provides an efficient and standardised way to test the design on an emulation platform."

Importantly, Aldec provides simulator and hardware boards with software that automates (design) mapping to FPGAs. In addition, thanks to Universal Verification Methodology (UVM), SCE-MI methodologies and supporting hardware/interfaces, it is possible to move freely between hardware simulation, emulation and system prototyping.

Moreover, Aldec's HES-7 boards can be used in different configurations at different phases of a project. For example, four boards (with two Xilinx Virtex-7 All Programmable FPGAs each) could be used by four engineers (hardware or software) as desktop prototyping platforms; to work on separate parts of the design. Moving towards system integration, a backplane can be used to connect the four HES-7 boards together; delivering the equivalent of 96 million ASIC gates.

Majkowski's presentation will cover an overview on transaction-based verification technologies, including SCE-MI macro-based and Direct Programming Interface (DPI) function-based synthesisable transactors, eliminating communication bottlenecks that could compromise the performance of hardware emulation systems. Real-life use cases will be shown, as well as two detailed customer case studies on transaction-based verification of large ASICs.

- Clive Maxfield
??EE Times





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