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IEEE 1149.1-2012 JTAG standard receives 85% ballot vote

Posted: 09 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:JTAG? IP blocks? on-chip tests?

Intellitech Corporation has secured support of the 1149.1-2012 JTAG standard with 85 per cent of votes cast by the IEEE ballot group in a recent International Test Conference. The standard incorporates industry best practices for enabling IC test re-use from silicon to systems.

"Our ballot group consisted of a large cross section of the industry. Ballot members with affiliations from Alcatel-Lucent, AMD, ARM, Cadence, Cisco, Freescale, Intel, Intellitech, NXP, ST Microelectronics, Synopsys, Texas Instruments and Teradyne all voted with approval," said CJ Clark, Intellitech CEO and chair of IEEE 1149.1.

Structural and procedural description languages have been standardised to support re-use of on-chip infrastructure IP blocks such as MemoryBIST, IOBIST, Logic BIST, SERDES PRBS, droop injectors, temperature and voltage monitors. The hierarchical description extensions to 1149.1 BSDL allow self-contained infrastructure IP descriptions which can then be instantiated at higher levels.

A hierarchical documentation language, PDL (Procedural Definition Language), based on the open source Tcl allows the IP vendor to describe the necessary steps to configure the IP via JTAG, initiate tests, and retrieve the results. The standard describes eight foundational instructions which provide support for programming I/O, tracking die through a unique ID, and executing on-chip tests in-situ without the integrity of the tests being impacted by the IC ecosystem.

The standard reaches a critical balance for the system integrator, the IC purchaser, and the IC vendor. There are rules and documentation requirements which protect the system integrator and rules which protect the IC vendor from false indictments of the IC in the field.

IEEE 1149.1-2012 now describes IEEE 1500 Wrapper Serial Port architectures and provides 1149.1 TAP access to those IEEE 1500 serial ports. A new synergy exists between the standards where 1149.1-2012 domain control enables the fixed IEEE 1500 bus to be segmented through power domains or stacked die. The capability enables IEEE 1149.1-2012 as "3D-SIC ready"; a stack using 1149.1 and 1500 can be described with a single BSDL and a package file for each 1500 wrapped die.

Since major EDA companies support IC test through IEEE 1500, incremental changes can be made to EDA tools to take advantage of the new on-chip structures and higher level of abstraction provided by 1149.1 BSDL and PDL. These languages would not replace but complement IEEE 1450.6 CTL.





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