TI's SoCs prepped for purpose-built ARM servers

Texas Instruments plans to extend ARM into its "purpose-built servers" while also providing networking gear with a new set of six 28nm System on Chips (SoCs). ARM Cortex A15 and TI C66x DSPs are used in the Keystone chips along with TI security and networking blocks.

Tom Flanagan, TI's director of technical strategy for multi-core processors, stated that the real opportunity for them is to off load some of the processing general purpose servers do. In some cases people may use ARM cores for classic server apps, but that isn't the company's main goal.

TI hopes to win sockets in systems designed to handle media processing, video analytics, industrial imaging and control and other high performance computing jobs suitable for its DSPs.

The new chips mark the first time TI has gone after routers and switches in a focused way. It faces a broad set of competitors including Cavium, Freescale and LSI who are also creating SoCs with ARM cores and with their own home-grown accelerators.

"OEMs are looking to move anything they can into a more open environment so they are pretty attracted to ARM cores," Flanagan said.

TI differentiates its parts in several ways. It uses a 256bit interface from the cores to the SoC clocked at the full 1.4GHz data rate of the cores. Several vendors use 128bit interfaces clocked at a third to half the core rate.

In addition, TI packs as much as 18 MB of aggregate memory on its high-end SoCs. The company claims it is also unique in supporting 1 and 10 Gbit Ethernet MACs in its chips.

At this stage, TI is not saying much about its road map for the SoCs. "We're looking at 64bit cores," he said.

The maximum performance per Watt of the 64bit ARM A53 core is "more philosophically in line with what like to do," he said. But TI is still "doing the math" about how it will compare with the A57 and whether 28 or 20 nm process technologies will be the best target.

"The 64bit ARM cores are not widely available until 2014, so we have time on this," he added.

Meanwhile, the new Keystone chips sample in December in versions consuming from 6 to 13W. High-end versions use up to four A15s and six C66x DSPs to deliver up to 352 GMACs and 19,600 Dhrystone MIPS.

Two of the chips will use just one DSP core for workloads with less heavy signal-crunching requirements. Two low-end parts will not contain any DSPs and will focus on jobs such as networking and industrial sensor nets.

Prices start at $30 in thousands for chips clocked at 850MHz. The high-end members of the new family are sampling now with volume production before June. Middle and low-end versions will sample in the second half of 2013.

- Rick Merritt
??EE Times