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Analyst puts Haswell under microscope

Posted: 16 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Haswell?

For those curious as to what Haswell has to offer, microprocessor analyst David Kanter provides a detailed description of the architecture of the first chip designed by Intel for its 22nm FinFET process.

Kanter describes Haswell as "a dual-threaded, out-of-order microprocessor that is capable of decoding five instructions, issuing four fused micro-ops and dispatching eight micro-ops each cycle."

Haswell will emerge next year, probably ahead of most of the 64bit ARM chips and in tandem with AMD's next generation cores such as Steamroller. Ultimately, it will appear in everything from tablet SoCs to server CPUs. (See Intel pitches Haswell as next-gen tablet platform.)

At this stage, Kanter could only do a paper analysis of the microarchitecture. It will be many months before we see test results on working Haswell chips.

That said, Kanter was able to make some interesting high-level projections based on his deep dive into the workings of the chip. "We estimate that a Haswell core will offer around 10 per cent greater performance for existing software, compared to [Intel's current] Sandy Bridge [processors, and] for workloads using the new extensions, the gains could be significantly higher," he said.

In theory, some instruction set extensions could double performance on some jobs, and a new transactional memory feature could provide 30 per cent gains on other operations, he said.

Measured next to its traditional x86 competitor, "Intel is already far ahead of AMD in terms of CPU performance," writes Kanter. "The performance gap should narrow given the scope of opportunities for AMD to improve, but Haswell will continue to have significant advantages."

Haswell will come in 10W versions for tablets where it will compete with 4W ARM-based SoCs, Kanter added. We will need to wait for working silicon to know relative performance/Watt efficiency of Haswell against the ARM chips, he said.

Indeed, there will be plenty of tales to tell once real chips get out of the lab next year. Until then, microprocessor aficionados can enjoy Kanter's block-by-block tour of the architecture.

- Rick Merritt
??EE Times





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