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Memory to make a splash at ISSCC 2013

Posted: 21 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:PCRAM? ReRAM? STT-MRAM? smart algorithms?

Relentless scaling advances will highlight memory papers during next year's International Solid State Circuits Conference (ISSCC), but it may be breakthroughs in off-beat memory architectures that raise a few eyebrows.

Memory subcommittee chair Kevin Zhang of Intel notes in his memory overview, "We continue to see progressive scaling in embedded SRAM, DRAM, and floating-gate based Flash for very broad applications. However, due to the major scaling challenges in all mainstream memory technologies, we see a continued increase in the use of smart algorithms and error-correction techniques to compensate for increased device variability."

Memory capacity trend

Memory capacity trend of emerging non-volatile memories

However, "Emerging memory technologies are making steady progress towards product introductions, including PCRAM and resistive random-access memory (ReRAM), while STT-MRAM is beginning to become a strong candidate for both stand-alone and embedded applications."

Revving ReRAM
One of the standout papers for the memory sessions comes from Toshiba and Sandisk, who will describe a 32Gb ReRAM test chip developed in 24nm process, with a diode as the selection device.

The allure of alternative non-volatile memories has been high cycling capability and lower power per bit in read/write but their densities don't compete with NAND flash. ISSCC organisers noted that the highest density for a single chip published at last year's ISSCC is 64Mb for ReRAM and 8Gb for PRAM, while NAND can reach up to 128Gb.

The Sandisk-Toshiba test chip is a metal-oxide-based ReRAM is based on 24nm technology node with a diode as the selection device and a 2-layered architecture. Apparently as part of the stacking, a number of circuits are tucked under the array, including the selection transistor or decoder, bias-control circuit,

sense amplifier, page buffer, read/write control circuit and voltage regulator drivers, improving the array efficiency, according to a preview of the paper.

Sizzling SRAM; bandwidth busters
"ReRAM now has the opportunity to be adopted as a storage-class memory competing with the existing NAND Flash memories for nonvolatile mass storage applications," the paper's presenters argue.

Another ReRAM paper, from Panasonic, presents an ReRAM filament-scaling forming technique and level-verify-write scheme with endurance over 107 cycles for a 16nm cell. It is realised within a 1T1R ReRAM array.

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