Using JESD204B for wideband data converter apps(2)

Medical imaging systems: Medical imaging systems including ultrasound, computational tomography (CT) scanners, magnetic resonance imaging (MRI), and others generate many channels of data that flow through a data converter to FPGAs or DSPs. Continually increasing I/O counts are driving up the number of components by requiring the use of interposers to match FPGA and converter pin out and increasing PCB complexity. This adds additional cost and complexity to the customer's system that can be solved by the more efficient JESD204B interface.

Radar and secure communications: Increasingly sophisticated pulse structures on today's advanced radar receivers are pushing signal bandwidths towards 1GHz and higher. Latest generation active electronically scaled array (AESA) radar systems may have thousands of elements. High bandwidth SERDES-based serial interfaces are needed to connect the array element data converters to the FPGAs or DSPs that process incoming and generate outgoing data streams.

Choosing between series LVDS and JESD204B
In order to best select between converter products that use either LVDS or the various versions of the JESD204 serial interface specification, a comparison of the features and capabilities of each interface is useful. A short tabular comparison is provided in the table.

Table: Comparison between the serial LVDS and JESD204 specifications.

At the SERDES level, a notable difference between LVDS and JESD204 is the lane data rate, with JESD204 supporting greater than three times the serial link speed per lane when compared with LVDS. When comparing the high-level features like multi-device synchronisation, deterministic latency and harmonic clocking, JESD204B is the only interface that provides this functionality. Systems requiring wide bandwidth multi-channel converters that are sensitive to deterministic latency across all lanes and channels won't be able to effectively use LVDS or parallel CMOS.

LVDS overview
Low-voltage differential signalling (LVDS) is the traditional method of interfacing data converters with FPGAs or DSPs. LVDS was introduced in 1994 with the goal of providing higher bandwidth and lower power dissipation than the existing RS-422 and RS-485 differential transmission standards. LVDS was standardised with the publication of TIA/EIA-644 in 1995. The use of LVDS increased in the late 1990s and the standard was revised with the publication of TIA/EIA-644-A in 2001.

LVDS uses differential signals with low-voltage swings for high-speed data transmission. The transmitter typically drives ±3.5 mA with a polarity matching the logic level to be sent through a 100? resistor, generating a ±350-mV voltage swing at the receiver. The always-on current is routed in different directions to generate logic ones and zeros. The always-on nature of LVDS helps eliminate simultaneous switching noise spikes and potential electromagnetic interference that sometimes occur when transistors are turned on and off in single-ended technologies. The differential nature of LVDS also provides considerable immunity to common-mode noise sources. The TIA/EIA-644-A standard recommends a maximum data rate of 655Mbit/s, although it predicts a possible speed of over 1.9Gbit/s for an ideal transmission medium.

Figure 2: Challenges in system design and interconnect using parallel CMOS or LVDS.

The huge increase in the number and speed of data channels between FPGAs or DSPs and data converters, particularly in the applications described earlier has created several issues with the LVDS interface (figure 2). The bandwidth of a differential LVDS wire is limited to about 1.0Gbit/s in the real world. In many current applications, this creates the need for a substantial number of high-bandwidth PCB interconnects, each of which is a potential failure point. The large number of traces also increases PCB complexity or overall form factor, which raises both design and manufacturing costs. In some applications, the data converter interface becomes the limiting factor in achieving the required system performance in bandwidth hungry applications.

JESD204B overview
The JESD204 data converter serial interface standard was created by the JEDEC Solid State Technology Association JC-16 Committee on Interface Technology with the goal of providing a higher speed serial interface for data converters to increase bandwidth and reduce the number of digital inputs and outputs between high-speed data converters and other devices. The standard builds on 8b/10b encoding technology developed by IBM that eliminates the need for a frame clock and a data clock, enabling single line pair communications at a much higher speed.