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Cadence synthesis tech eases Renesas ASIC design

Posted: 28 Nov 2012 ?? ?Print Version ?Bookmark and Share

Keywords:ASIC design? Renesas? Encounter RTL Compiler? place-and-route cycles?

Cadence Design Systems Inc. has revealed that Renesas Micro Systems Co. Ltd has adopted the Cadence Encounter RTL Compiler for synthesis. According to the company, it claims to improve utilisation by 15 per cent, area reduction by 8.4 per cent, quick turnaround time and cost reduction for complex ASIC designs.

"Renesas Micro Systems has been working very closely with Cadence to develop best-in-class netlist analysis flows that provide early insights into potential structural issues and inefficiencies. Encounter RTL Compiler solved a problem we had been grappling with for a long while," noted Kazuyuki Irie, chief professional, SoC development division of Renesas. "With our prior flow, we were frustrated with all the additional place-and-route cycles we were burning each time we analysed and resolved problems with hot spots and routability. The Cadence technology offers us a faster and more cost-efficient way to get to production silicon."

In today's ASIC design development, there is an increased demand for ultra-large-scale, high speed, and complex designs, and Renesas is focused on high-density layout, high speed and short turnaround time for its ASIC designs. In the past, it was difficult for company engineers to fix serious routability issues after running place and route tools, resulting in longer turnaround times. If engineers identified hot spots, they were forced to run place and route tools to assist with maximum utilisation, adjustment of placement congestion, floorplanning and circuit optimisation, said the company.

Encounter RTL Compiler enables an environment for the structural analysis of a netlist early in the flow. This allows Renesas engineers to identify problematic structures in their designs before conducting place and route. By applying this methodology, they have been reducing turnaround time and easing congestion hot spots, which allows them to further improve utilisation and reduce the die size, detailed the firms.





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