Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Amplifiers/Converters

Examining successive-approximation register ADC

Posted: 05 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:Successive-approximation register? analogue-to-digital converters? driving stage?

Successive-approximation register analogue-to-digital converters (SAR-ADC) are frequently the architecture of choice for medium-resolution applications. SAR products on the market can operate at maximum sample rates up to several megahertz. However, designers match their application needs with much slower SAR-ADCs in an effort to reduce cost and layout headaches. On the market, the SAR-ADC resolutions range from 8 to 18 bits.

This style of device has a small form factor and provides low-power consumption, which is critical for battery-powered applications. In this article, we examine the inner workings of the SAR-ADC and the converter's driver requirements.

How the SAR-ADC works
The SAR-ADC (figure 1) captures an analogue voltage signal, converts that signal to a digital word. The analogue signal is captured with either an external sample/hold device or the SAR-ADC's internal sample/hold function. The SAR-ADC compares this input voltage to known fractions of the converter's external or internal voltage reference (VREF). This reference sets the full-scale input voltage range of the converter. Modern SAR-ADCs use a capacitive, digital-to-analogue converter (C-DAC) to successively compare bit combinations and set or clear appropriate bits into a data register.

Figure 1: This is a model of the internal sampling mechanism for a modern SAR-ADC 16bit converter. After acquiring the signal at VS, the chip select transitions from high to low and opens the input switch (S1).

At the input of a SAR converter, the input signal first sees a switch. Notice, that a closed switch creates a switch resistance (RIN) in series with a capacitive array. The top side of these capacitors connects to the inverting input of a comparator. The bottom side can tie into the input voltage, the voltage reference (VREF), or ground (VC). Initially, the bottom side connects to the input signal, VS. Once the capacitive array completely acquires the input signal, the input switch (S1) opens and the converter starts the conversion process.

During the conversion process, the bottom side of the MSB capacitor connects to VREF while the other capacitors connect to VC (or system ground). This action redistributes charge among all the capacitors. The comparator's inverting input moves up or down in voltage according to charge balancing. If the voltage at SC is greater than half VREF, the converter assigns "0" to the MSB and transmits that value out of the serial port. If this voltage is less than half VREF, the converter transmits a "1" out of the serial port, and the converter connects the MSB capacitor to VC. Following the MSB assignment, this process repeats with the MSB-1 capacitor. Note that figure 1 does not show the MSB-1 capacitor, but its value is 8C.

The time required for the SAR-ADC conversion process to occur consists of the acquisition and convert time. At the conclusion of the total conversion process, the SAR-ADC goes into a sleep mode.

Driving your SAR-ADC
The optimised ADC driver circuit in figure 2 uses an operational amplifier (op amp) to separate the SAR-ADC from high impedance input source, VSIG. The following R/C low-pass circuit (RISO and CISO) performs functions going back to the op amp and forward to the SAR-ADC. RISO keeps the amplifier stable by isolating the amplifier's output stage from CISO. CISO provides a nearly perfect and stable input source to the SAR-ADC. This CISO tracks the voltage's input signal and provides the appropriate SAR-ADC charge during the converter's acquisition time.

Figure 2: The SAR-ADC application design requires a driver circuit (op amp, RISO, and CISO) to ensure that the ADC has a stable input signal during the converter's acquisition period.

As you design your SAR-ADC circuit, first determine what your input signal looks like in terms of the bandwidth and full-scale range. Then, your selected SAR-ADC should match the bandwidth of the input signal per nyquist. This converter should also have the appropriate resolution for your system. In this design, the critical SAR-ADC specifications are the cumulative value of the capacitive array, CIN (which is equivalent to the SAR-ADC's input capacitance), the converters full-scale input range, and the acquisition time (tAQU).

Defining RISO, CISO
Now we move on to defining RISO and CISO by determining their values. The figure 3 scope capture shows the input charge-injection transients of a SAR-ADC (ADS8326). In this measurement, there is a 10 kOhm resistor between the amplifier buffer and the SAR-ADC (Ch1). The start-conversion or chip select signal appears on the top curve (Ch4). Be aware that the input impedance presented to a SAR converter should never be as high as 10 kOhm but this allows us to see the high-frequency current spikes at this SAR-ADC's input.

1???2?Next Page?Last Page

Article Comments - Examining successive-approximation r...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top