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Synchroniser with programmable MTBF capabilities

Posted: 07 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:system on chip? Metastability? flip-flop?

Synchroniser circuits are commonly used in modern system on chip (SoC) designs to facilitate the reliable data transfer between independent clock domains [1, 2]. As design geometry shrinks and clock speeds approach the gigahertz range, the design of synchroniser circuits becomes a challenging task. Metastability (the ability of a digital electronic system to persist for an unbounded time in an unstable equilibrium or metastable state) is a key factor to be considered. The mean time between failures (MTBF) value, which is a figure of merit related to metastability, degrades sharply when input clock and/or data frequency is increased, as per the synchroniser MTBF formula given in this equation:

In the equation, Fclk and Fdata are input clock and data frequency respectively, tMETA is the time delay allowed for metastability to resolve itself, C1 is a constant representing the metastability catching setup time window and C2 is a constant describing the speed with which the metastable condition is resolved.

The possible ways to increase MTBF are by cascading more flip-flops in the synchroniser circuit or by running the synchroniser at a slower frequency. In both the cases, tMETA value increases and the MTBF value increases exponentially as per equation (1). The proposed synchroniser enhances the MTBF value by dividing the high frequency input clock by a user defined division ratio, N.

With a standard two flip-flop synchroniser, the delay introduced between the input and the synchronised output is equal to one flip-flop's clock-to-output delay (Tcq) plus the delay of an AND gate (Tand). To increase the MTBF, if a standard two flip-flop synchroniser is run with a divided clock, the total delay between the input and the synchronised output will become 2*Tcq + Tand. The additional Tcq delay is contributed by the clock divider circuit. Due to this extra Tcq delay of a flip-flop, a glitch may appear in the synchronised output if the total delay is more than the OFF period of the input clock.

The situation will further degrade if the input clock duty cycle is more than 50%, further reducing the OFF period of the input clock. In the proposed synchroniser, instead of an extra Tcq delay contributed by the clock divider circuit, only a NAND gate delay (Tnand) is added, which is much less as compared to Tcq. The typical values of Tcq and Tnand are approximately 300ps and 30ps respectively in 90nm CMOS technology. Thus, the total delay becomes Tcq + Tand + Tnand and the proposed synchroniser is able to run at a much higher frequency as compared to a standard two flip-flop synchroniser.

Circuit description
Figure 1 shows the block diagram of the proposed synchroniser. The asynchronous input data is captured by the input flip-flop (FF). The output of the input FF is captured by a standard two flip-flop synchroniser, running on a divided input clock.

Figure 2 shows the circuit diagram of the proposed synchroniser. The input clock, clk, goes to a divide by 4 circuit (N=2) composed of flip-flops FF4 and FF5. This divider can be made programmable to divide by N=2, 3, 4 etc. The flip-flops FF2 and FF3 form a standard two flip-flop synchroniser which is driven by the rising edges of the generated clock, clk_gated. The frequency of clk_gated is equal to one-fourth of the frequency of clk.

As shown in figure 2, the delay between clk and clk_gated is equal to the delay of a NAND gate, NAND1. The overall MTBF of the synchroniser will be the MTBF of FF1 (MTBF1) times the MTBF of the synchroniser composed of FF2 and FF3 (MTBF2).

Figure 1: Block diagram of the proposed synchroniser.

Figure 2: Circuit diagram of the proposed synchroniser.

Because clk and data are asynchronous, FF1 can enter into a metastable state whenever a transition at its data inputwith respect to a transition at its clock inputhappens in the setup-hold window, which is typically 100ps-150ps. Similarly, FF2 can enter into a metastable state whenever a transition at data_mid1 with respect to a transition at clk_gated happens in the setup-hold window.

It is clear from figure 2 that even if FF2 output, data_mid2, becomes metastable, the time it will get to resolve the metastable state will be four times the time period of clk. Also, since the frequency of clk_gated is one-fourth of clk, the overall MTBF improvement will be 4e4 (~218.4) times as compared to a standard two flip-flop synchroniser. Qualitatively, because of quadruple increase in tMETA, probability of FF3 going into metastable state decreases significantly. In general, dividing the input clock by N improves the overall MTBF by NeN. However, an increase in N also increases the number of clk cycles required before the synchronised output, data_sync, appears. The number of clk cycles required depends upon relative timing of data transition at data and data_mid1 with respect to clk and clk_gated respectively, and whether FF1 and/or FF2 entered into a metastable state.

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