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Intel tweaks 22nm tri-gate SoC for ultra-low leakage

Posted: 12 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:tri-gate? FinFET transistors? SoC?

Intel unveiled the latest modification to its 22nm tri-gate SoC during the annual International Electron Devices Meeting. The new SoC has been scaled down to a more mobile, ultra-low leakage version.

The change means Intel will now be able to boast product support from high performance servers down to cell phones on a tri-gate 22nm process, with transistors covering a wide range of performance barriers. It also includes high voltage I/O transistors, precision resistors, capacitors and inductors that were not included on the original CPU version of the chip introduced back in June. The SoC's will be ready for high volume manufacturing in 2013, Intel senior fellow Mark Bohr said.

Intel had tended to focus heavily on performance, but is now looking to widen its transistor scope. On the performance side of the scale is the CPU version of Ivy Bridge, which also exhibits higher power leakage. On the lower end of the scale, however, Intel is seeking to offering a range of choices.

22nm SoC transistor options

22nm SoC transistor options. Ready for high volume manufacturing in 2013.

"There isn't just one version of our SoC technology," Bohr said. "We [will] offer a rich menu of options to pick and choose from, both different transistor options and different interconnect options," said Bohr.

Why FinFET is good for analogue design
Bohr said it was now abundantly clear that 22nm tri-gate SoCs outperformed 32nm planar devices by a margin of 20 to 65 per cent, while covering four different orders of magnitude in current leakage.

Intel said its 22nm tri-gate product also exhibits superior short channel control, with optimum sub-threshold slope and drain-induced barrier lowering (DIBL). The sub-threshold slope allows for low leakage but could also function well at low voltage, making them "much better than the very best planar devices," Bohr added.

Bohr said the low numbers for DIBL seen in testing were a measure of good performance in short channel control, with the new SoC pulling in DIBL numbers of 30 to 35mVs, while comparable products had DIBL's closer to the 100mV range.

Bohr said that when Intel had first announced it would be using tri-gate devices, other companies had argued that FinFET transistors would not aid analogue design. "Well, they're wrong," declared Bohr.

For analogue designers, he asserted, an important transistor metric is transconductance by power out (GM x Rout). Bohr said that while this value had been steadily degrading over the past few generations, it had shot up again in 22nm tri-gate SoCs, making it easier for analogue circuit designers to use than Intel's previous three generations of planar technology.

Bohr also touted the technology's advanced passive features, including precision resistors, MIM capacitors and high Q inductors.


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