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Toshiba says MRAM future of mobile processors

Posted: 13 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:STT-MRAM? SRAM? cache applications? mobile processors? tablets?

A prototype spin transfer torque magneto resistive random access memory (STT-MRAM) has been developed by Toshiba. The company expects this technology to eventually replace SRAM in cache memory for mobile processors within smartphones and tablet computers.

A subject of a paper at IEDM 2012, the STT-MRAM structure has the lowest power consumption yet reported and is about one-tenth that of prior reported prototypes. Because of this Toshiba reckons it is the first MRAM able to compete with SRAM for cache applications and the company said it intends to accelerate R&D to that end.

The improved structure is based on perpendicular magnetisation. This can be reversed at lower energy than in-plane magnetisation, making it possible to program data at lower currents and fabricate smaller memory cells. The latest work by Toshiba takes the element miniaturisation below 30nm. The memory circuit has no leakage current both in operation and in standby, Toshiba said.


Figure 1: Toshiba STT-MRAM structure with vertical magnetisation and 30nm memory size.

The STT-MRAM structure provides an MRAM that can be of lower power consumption than its SRAM equivalent. Toshiba has also written a simulation of how such an STT-MRAM would perform as cache memory in a mobile processor application and recorded a 66 per cent reduction in power consumption for standard operating functions.

The memory is the result of the "Normally-off Computing" project funded by Japan's NEDO (New Energy and Industrial Technology Development Organisation). Toshiba is presenting three papers on the STT-MRAM at IEDM.

- Peter Clarke
??EE Times

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