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Impact of crystal electrodes on PCM (Part 2)

Posted: 18 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:phase change memory? germanium antimony tellurium? extrapolation?

Although phase-change memory (PCM) technology is touted to show promise for next-generation storage applications, challenges remain, one of which is the impact of heat on data retention lifetime of PCM devices. While the effect is a function of the material composition, it now appears it might also be caused by elements of the device structure: in particular, the crystal electrodes. Part 1 of this article established the seeded-bridge model, which allows the novel use of elevated-temperature data-retention (ETDR) results to explore the "set" parameters of PCM devices and exposed the possible negative link between scaling and poor ETDR performance. Here in part two, we will review published ETDR results to see whether the model holds true.

The accepted way of presenting ETDR data is to plot the time to failure t in the form log t = f(1/kT), where t = to exp(E/kT), k is the Boltzmann constant, T is temperature. This presents the data as a straight line whose slope corresponds to the activation energy E. I extracted ETDR test data from published work of Samsung, S. K. Hynix and IBM [2 ,6, &7] and carefully transcribed them into figure 5. As described in Part 1, I then back extrapolated the data over several decades as a means of exploring the performance (temperature and set times) at the 100 ns scale. Note, results for IBM's "golden composition" were not available in the normal ETDR test data form described above, so the data used for that material in figure 5 is an estimate based on other similar published results.

All three devices represent the leading edge of PCM device development both in terms of device structure and active material compositions. The exact compositions of the material are not available but they are different germanium antimony tellurium (GST) compositions, that is GST225 either antimony-rich, nitrogen-doped, or germanium-rich. Also shown, as insets in figure 1, are simplified cross section diagrams that illustrate each device structure.

Figure 1: The ETDR results from published works of Samsung, IBM, and SK Hynix in the normal form of time to failure t = (1/kT) when back extrapolated to a set time of 100 ns (horizontal dot-dash line) and shifted for complete crystallisation (as marked) the prediction of the seeded-bridge model is set temperature and required power will increase as ETDR performance improves.

Plotting the results for the three materials and associated ETDR characteristics on the same axis serves to highlight the progress made in the ETDR performance of PCM materials, from t=10 years at 85�C to now, with claims of more than 100 years at that temperature. If the seeded bridge model is a correct description of the elevated temperature data loss and the set processes, the back extrapolation suggests that the improved materials will extract a penalty in terms of the trade-offs that must be made among temperature, "set" time, and power. For example, in order to achieve the highest data write bandwidth (shortest "set" time) for the material with the higher crystallisation temperature, it will require a higher "set" current in order to raise the internal temperature of the device to achieve that "set" time, with the result of an undesirable increase in overall power dissipation for the PCM memory chip.

Interpreting the data
Although the actual temperatures have not been measured, nor is it known how close the "set" pulse is to optimum, the "set" pulse widths (times) and temperatures that result from the back-extrapolation an shown in figure 1 are not grossly out of line with expectations. At a first glance, the results of the back-extrapolation would suggest that the seeded-bridge model for the PCM set process that was developed in Part 1 is valid and no other types of crystallisation processes, such as electric field or current driven electro-crystallisation, are involved or are playing a significant role in the PCM "set" process.

While there are lithographic node differences and a number of structural differences such as volume of material involved, thermal barriers, and confining electrodes, the differences in pulse widths of set time ts=300 ns for Hynix and ts=150 ns for Samsung are in broad agreement with what would be expected if the back-extrapolation-based model is valid and higher temperatures for crystallisation are required. The actual operating "set" and "reset" pulse widths and currents used for the devices on which this analysis is based are shown as annotations in figure 1.

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