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IBM showcases 3D server chip stacks

Posted: 14 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:45nm processors? DRAM? 3D stacking? Hybrid Memory Cube? Moore's law?

IBM has provided an depth look on its 3D chip stacks at the International Electron Devices Meeting this week. The tech giant also gave an update about its work on stacks of 45nm server processors with memory card transceivers.

"As scaling saturates, and lithography sputters to a grinding halt, these orthogonal scaling techniques will assume even more importance and continue to keep Moore's 'law' alive," wrote Subraman S. Iyer, a senior IBM technologist in the IEDM paper to be presented on Dec. 12.

The paper shows IBM's road map extending from embedded DRAM to various 3D stacks with and without interposers using face-to-face and back-to-back stacks. In a separate paper, IBM disclosed the top two layers of metal in its new 22nm process are optimised for use with through silicon vias needed for 3D stacks.

Big Blue has long been expected to be among the early users of 3D stacking to pair its server CPUs with memories for performance and power advantages. It has been collaborating with Micron on the Hybrid Memory Cube, a memory stack for just such applications.

"Embedded DRAM, 3D stacking, interposers and wafer-to-wafer integration are intrinsic to this [IBM] roadmap," Iyer's paper said.

3D Stack

2 Terabit/s throughput
The paper shows IBM's road map extending from embedded DRAM to various 3D stacks with and without interposers using face-to-face and back-to-back stacks. In a separate paper, IBM disclosed the top two layers of metal in its new 22nm process are optimised for use with through silicon vias needed for 3D stacks.

"Embedded DRAM, 3D stacking, interposers and wafer-to-wafer integration are intrinsic to this [IBM] roadmap," Iyer said..

In one example, a 45nm SOI-based processor with eDRAM is stacked with two SiGe BiCMOS transceiver chips. "The bandwidth between chips exceeds 2 Tbit/s, far greater than achievable by either ceramic or organic interposers," Iyer wrote.

"This interposer technology which can also include decoupling capacitors for mid frequency power supply noise reduction is a key feature of the next step of the evolution of the embedded memory roadmap," he added.

IBM was quick to caution that "die-to-die 3D integration is a tedious process and is limited in the ability to achieve dense inter-die connections...but multi GB [memory] stacks can be integrated with the processor cache stack on a silicon interposer."

Iyer said IBM is using so-called fat copper wires for TSVs. Although nthey have a four-fold difference with silicon in their thermal coefficient of expansion "control of Cu microstructure can minimise the deleterious effects of this large mismatch," Iyer wrote.

"The stacking process is very sensitive to die warpage and the handling of thin die and controlling their warpage are key challenges," he added.

- Rick Merritt
??EE Times





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