Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Manufacturing/Packaging

Panel: No single approach in future of ICs

Posted: 17 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:FinFETs? planar silicon? tri-gate?

Panelists participating in an IEDM debate concerning the future of semiconductor technology argued that amid a wide range of new structures and materials, each process has its pros and cons.

"It's clear planar silicon as we know it ends at about the 20nm node, then there will be a race to different architectures and materials or combinations of both," said Suresh Venkatesan, senior vice president of technology development at Globalfoundries, moderating an evening panel at the International Electron Devices Meeting.

An IBM expert challenged that statement, showing a 10nm planar process.

Panelists argued for an assortment of options including FinFETS, germanium, III-V materials, tunnel FETs, nanowires and fully depleted silicon-on-insulator. All sides agreed just what defines a new node is increasingly unclear.

"Any time we talk about new nodes, we should wash our mouths out with soap," said Scott Thompson, chief technologist of start-up SuVolta and a former Intel fellow. Engineers ignore traditional metrics, saying "Intel's 22nm node is really 26nm, so if Intel does new math, so will we," he said.

"The next node after 14nm will be some small number, but there's no real pitch scaling," Thompson added. "Pitch scaling will slow, but we will still have smaller number nodes anyway," he said. (See FDSOI workshop reveals next nodes at 14nm, 10nm.)

Fur flies over FinFETs
Intel jump started the FinFET approach with its new 22nm tri-gate process, but it is not delivering on its promise, asserted an IBM process technology expert. (See Intel tweaks 22nm tri-gate SoC for ultra-low leakage.) Intel's Ivy Bridge chips made in the process deliver just 20 per cent power reductions compared to 35 per cent drops with the former node, said Ghavam Sahidi, a fellow at IBM Research.

"The real numbers are not very impressive, IBM got much better numbers and Intel's own 45- and 65-nm numbers were better," he claimed.

Sahidi blamed parasitics that resulted from Intel's decision to dope the FinFET structures. "If they go down this path to 14 and 10 nm of doping, it gets worseyou have to be un-doped," Sahidi said.

Thompson of SuVolta agreed. "I think Intel went down a path of un-doped fins, but I think they couldn't solve their problems, so they went into production with doped fins and sloped horribly," Thompson claimed. "I think that structure will not give the power or performance people expect and the right thing to do is an un-doped fin," he said.

1???2?Next Page?Last Page

Article Comments - Panel: No single approach in future ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top