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Easing system simulation with hardware models

Posted: 24 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:System simulators? RTL simulation? IP block?

System simulators are now gaining more importance in the FPGA and ASIC verification process, particularly for system-on-chips (SoCs) with performance-critical hardware accelerators and tightly-coupled embedded software. Cycle accuracy (CA) of the peripheral hardware is often a requirement or very desirable in many cases, especially if greater simulation performance over RTL simulation can be achieved. Some examples include:

???Detailed performance and utilisation of system interconnect, based on the actual hardware implementation running with its embedded software.
???Implementation of low-level drivers and firmware, which require register maps and may rely on exact latency and flow control behaviour of the peripheral.
???Software optimisation, which can be particularly important for algorithm hardware accelerators, codec development, as well as in cases where hardware and software are tightly coupled and there is a critical overall performance goal in latency, throughput, etc. In such scenarios, estimates by ISS and TLM can be off by a factor of three, resulting either in wasted silicon or chips that cannot meet their required performance.

Problem: Creating C-models of custom hardware
When designing custom hardware blocks in RTL, or using 3rd party RTL, the creation of a C model is often impractical due to the time and effort required. Also it requires a significant level of expertise in model coding (C++ or SystemC), model verification, and protocols, if standard interface protocols are used in the IP block. These are all obstacles in creating an effective system model that includes a custom hardware block.

Automatic C-model generation
Synopsys' Synphony Model Compiler tool can automatically create hardware-accurate C models of designs using RTL, high-level datapath models in Simulink, or a mixture of both. The C models can be used in a variety of simulators like ModelSim/VCS, Simulink, SystemC or direct execution. Using transformation and modelling technology, they are touted to maintain bit and cycle accuracy at the inputs and outputs of the model while achieving high simulation speeds, especially for multi-clock (multi-rate) designs. As demonstrated in the next section, users may realise over a 100 X simulation speed-up while eliminating the effort to create and maintain models of their IP.

Figure 1: Block diagram of a digital down-converter design example.

Design example: Digital radio design example
The benefits of automatic C-model generation are illustrated using a Digital Down Converter (DDC) example. The DDC requirements include a frequency synthesiser, I/Q mixer, followed by a 5-stage CIC decimation filter, a 20th order low-pass compensation filter, and a 39th order matched filter to attenuate the out-of-band signals. A CPU interface (AMBA AXI3) is provided as an RTL block and provides the coefficients for the matched filter, the carrier frequency, and the initial carrier phase for QAM demodulation. The block diagram of the DDC is shown in figure 1.

High-level design and verification: The DDC is designed in Simulink using Synphony Model Compiler. The datapath is built with high-level blocks from the Synphony Model Compiler library, while the AMBA AXI3 CPU interface is written in Verilog RTL using the Synphony RTL Encapsulation block to instantiate it into the Simulink model.

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