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Explore the key features of delta-sigma ADCs

Posted: 28 Dec 2012 ?? ?Print Version ?Bookmark and Share

Keywords:delta-sigma ADC? SAR? signal conditioning?

The following digital / decimator (low-pass) filter preserves the input signal as well as attenuates this higher frequency noise. It also takes this sampled modulator data and converts it into a precise digital signal [3].

Programmable data rate
Many delta-sigma converters have a programmable data rate. The decimation ratio (DR) of a delta-sigma converter equals the number modulator samples per data output, or DR = Fs/Fd. Decimation ratio values range anywhere from four or eight (ADS1605) to 32,768 (ADS1256). The relationship between the output data rate and the sampling rate directly impacts the effective-number-of-bits (ENOB) at the converter's output.

Consider the output spectrum of a delta-sigma modulator (Fs) versus the digital / decimation filter (Fd) in figure 3. The modulator sample rate (Fs) shapes the quantisation bandwidth. The data rate (Fd) is always smaller than Fs, as in figure 3A and 3B. The signals from zero to Fd are included in the converter's output. Note the noise level in this frequency band. The ENOB describes noise and distortion in the converter's output data. The ENOB in Figure 3A is higher than the ENOB in Figure 3B [4].

Figure 3: The digital / decimation filter cut-off frequency (Fd) is lower than the modulator's sampling frequency (Fs). The modulator's integrator successfully shapes quantisation noise towards Fs.

Using digital process gain
mplementation of the SAR-ADC external, analogue-gain stage typically includes at least one, if not more, operational amplifiers. Designers use these amplifiers to gain and level-shift the analogue signal. The delta-sigma converter handles these analogue functions with an internal digital process gain. You can use the delta-sigma's process gain to create a 10-, 12-, or 16bit system with a 24bit converter. This eliminates the external gain and level shift circuits [5].

For instance, a noiseless 24bit delta-sigma converter has 4096 individual, 12bit converters across the converter's output range. Noiseless, 24bit delta-sigma converters are hard to find, but a delta-sigma converter with an effective resolution of 19.5bits (rms) is more realistic. Figure 4 shows the relationship between output codes and noisy bits of this realistic 24bit delta-sigma converter.

Figure 4: Capturing the right output codes of the 19.5bit (rms) delta-sigma converter can provide a level shift and process gain.

Figure 4 diagrams the technique used to absorb the analogue functions of gain and level-shift into the delta-sigma converter. Ignoring the most-significant-bits allows you to implement a level-shift function. Process gain is equivalent to an analogue gain by determining the location of the new MSB at the converter's output. A gain change is implemented by shifting the 12bit window in figure 4 to the right or towards the converter's least significant bit (LSB). Each one-bit shift to the right is equivalent to doubling the process gain. As in the analogue domain, an increase in process gain lessens the input range. In figure 4, you can increase the process gain to 64 or 128. This is equivalent to an analogue gain of 64 V/V or 128 V/V.

With this technique, you have the full resolution of 224 codes at our disposal. Select the ADC range portion and focus just on the area where the signal response is occurring. Note that you are trading off the loss of your 24bit converter's dynamic range with the elimination of the external analogue circuitry.

Delta-sigma converters are available with many additional features that make them ideal for data acquisition. Many of these types of converters include a programmable-gain amplifier (PGA) and input buffer that can further reduce the requirements for external signal conditioning. Some also have special features for sensor connections, like burnout current sources.

Delta-sigma converter applications have fewer components as compared to SAR-ADC circuits. While in operation, the delta-sigma ADC continuously oversamples an input voltage signal. The ADC then applies a digital filter on these samples to achieve a multi-bit, low-noise digital output. The byproduct of this algorithm is a higher dynamic range and lower output speeds. Many designers focus on the number of output bits that this type of converter can produce. However, the often overlooked hidden feature is process gain. This feature allows the designer to eliminate external analogue circuitry in these low-frequency signal chains.

1. "Delta-sigma antialiasing filter with a mode rejection circuit," Bonnie Baker,, September 17, 2012.
2. "Delta-sigma ADCs in a nutshell, part 2: the modulator," Bonnie Baker,, January 24, 2008.
3. "Delta-sigma ADCs in a nutshell, part 3: the digital/decimator filter," Bonnie Baker,, February 21, 2008.
4. "A glossary of analogue-to-digital specifications and performancecharacteristics," Bonnie Baker, Application Report (SBAA147B), Texas Instruments, October 2011.
5. "Take a risk; throw away those bits!," Bonnie Baker,, October 22, 2009.

About the author
Bonnie C. Baker is a Senior Applications Engineer at Texas Instruments.

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