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Efficient FSK/PSK modulation with multi-channel DDS

Posted: 17 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Frequency-shift keying? direct digital synthesiser? modulator?

Frequency-shift keying (FSK) and phase-shift keying (PSK) modulation schemes are utilised in digital communications, radar, RFID and many other applications. The simplest form of FSK uses two discrete frequencies to transmit binary information, with Logic 1 representing the mark frequency and Logic 0 representing the space frequency. The simplest form of PSK is binary (BPSK), which uses two phases separated by 180. Figure 1 illustrates the two types of modulation.

The modulated output of a direct digital synthesiser (DDS) can switch frequency and/or phase in a phase-continuous or phase-coherent manner, as shown in figure 1 (also see Ref. 1), making DDS technology well suited for both FSK and PSK modulation.

Figure 1: Binary FSK (a) and PSK (b) modulation.

This article describes how two synchronised DDS channels can implement a zero-crossing FSK or PSK modulator. Here, the AD9958 two-channel, 500-MSPS DDS is used to switch frequencies or phases at the zero-crossing point, but any two-channel synchronised solution should be capable of accomplishing this function. In phase-coherent radar systems, zero-crossing switching reduces the amount post processing needed for signature recognition of the target; and implementing PSK at the zero crossing reduces spectral splatter.

Although both of the DDS-channel outputs are independent, they share an internal system clock and reside on a single piece of silicon, so they should provide more reliable channel-to-channel tracking over temperature and power-supply deviations than the outputs of multiple, single-channel devices synchronised together. The process variability that may exist between distinct devices is also larger than any process variability you might see between two channels fabricated in a single piece of silicon, making a multi-channel DDS preferable for use as a zero-crossing FSK or PSK modulator.

Figure 2: Setup for zero-crossing FSK or PSK modulator.

A critical element of any DDS is the phase accumulator, which, in this implementation, is 32 bits wide. When the accumulator overflows, it retains any excess value. When the accumulator overflows with no remainder (figure 3), the output is precisely at phase 0, and the DDS engine starts over from where it was at time 0. The rate at which the zero-overflow is experienced is referred to as the grand-repetition rate (GRR) of the DDS.

Figure 3: Basic DDS with overflowing accumulator.

The GRR is determined by the rightmost nonzero bit of the DDS frequency tuning word (FTW), as established by the following equation:

GRR = FS/2n,

where FS is the sampling frequency of the DDS, and n is the rightmost nonzero bit of the FTW. For example, suppose a DDS with a 1GHz sampling frequency employs 32bit mark and space FTWs with the binary values shown. In this case, the rightmost nonzero bit of either FTW is the 19th bit, so GRR = 1GHz/219, or approximately 1907Hz.

How to implement
A DDS inherently switches frequency in a phase-continuous manner. This means that no instantaneous phase change occurs when the frequency tuning word changes. That is, the accumulator starts accumulating the new FTW from whatever phase position it was at when the new FTW was applied. Phase coherence, on the other hand, requires an instantaneous transition to the phase of the new frequency as if the new frequency had been present all along. Therefore, in order for a standard DDS to implement a phase-coherent FSK switch, the change from a mark frequency to a space frequency must occur when both frequencies have the same absolute phase.

To implement a zero-crossing switch in a phase-coherent manner, the DDS must make the frequency transition at 0 degrees (that is, when the accumulator overflows with zero excess). Therefore, we must determine the instants at which phase coherent zero-crossings occur. If the GRR of the mark and space FTWs are known, the smaller of the two GRRs (if different) will indicate the desired phase coherent zero-crossing point.

Three criteria are necessary for implementing a phase-coherent zero-crossing switch:
1. The ability to determine the smaller GRR of the mark and space FTWs associated with CH0 of figure 2.
2. A second DDS channel (CH1 of figure 2) synchronised to CH0 of figure 2 and programmed with an FTW having all zeros except for the one bit corresponding to the smaller GRR.
3. The capability to use the rollover of the second channel to trigger a frequency change on CH0 of figure 2.

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