Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Examine soft-core processors for embedded systems

Posted: 21 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:microprocessor? embedded system? FPGA? microcontroller?

When designing an embedded system in an FPGA, we will most likely need some form of "controller" in our system. This controller can be a simple microcontroller or a fully-fledged microprocessor running the Linux operating system. But before we make this decision, let's first consider the various options that are available to us.

One solution is to use an off-the-shelf (OTS) microprocessor mounted on the board and connecting to the FPGA using a standard bus like AMBA. In fact, this still appears to be the most commonly-used solution. There are times, however, where an OTS processor-based approach will not meet our requirements. An example would be an application that requires peripheral functionality that is not available in a discrete solution, or where board real estate is limited.

Another option is to embed a "hard" processor core on the chip. A hard processor core has dedicated silicon area on the FPGA. This allows it to operate with a core frequency similar to that of a discrete microprocessor. Examples of hard processor cores used in FPGAs are the PowerPC used in Virtex-4/5 and the ARM Cortex-A9 dual-core MCU used in the new Zynq-7000 All Programmable SoC from Xilinx.

Unfortunately, a hard processor core does not provide the ability to adjust it to better meet the needs of the application, nor does it allow for the flexibility of adding a processor to an existing FPGA design or adding an additional processor to provide more processing capabilities.

A soft-core processor solution is one that is implemented entirely in the logic primitives of an FPGA. Because of this implementation, the processor will not operate at the same clock frequencies or have the same performance of a discrete solution. In many embedded applications, however, the high performance achieved by the previous two processing options is not required, and performance can be traded for expanded functionality, reduced cost, and flexibility.

All the major FPGA vendors have soft-core processors in their product offerings and there are also a number of companies and organisations developing soft-core processors that are platform independent and can be implemented in any FPGA design.

Choosing a soft-core processor
When commencing an FPGA design project that will employ a soft-core processor, it can be hard to decide which processor to use. To help you with this decision and give you quick start guide, let's take a closer look at four soft-core processor to see which one would be most suitable for your platform. Here are the four candidates we will investigate:

???Nios II

Our system will be built on a standard FPGA development board. We will use the CAE tools that are suggested by the processor provider and try to use licence-free tools as much as possible. When there are no free tools available, we will use an evaluation licence from the FPGA vendor. The system must be able to run a Linux operating system and a Real Time Operating System (RTOS). The performance of the processor cores will be measured by using the benchmark program CoreMark.

CPU core benchmarking
Although it doesn't reflect how you would use a processor in a real application, sometimes it's important to isolate the CPU's core from the other elements of the processor and focus on one key element. For example, you might want to have the ability to ignore memory and I/O effects and focus primarily on the pipeline operation. CoreMark is capable of testing a processor's basic pipeline structure; it also provides the ability to test basic read/write operations, integer operations, and control operations.

Installing Linux
We will use the Linux distribution recommended by the processor vendor. An embedded system that is going to run Linux must include some specific hardware blocks. In a typical system we find the following:

???CPU with memory management unit (MMU)
???Instruction and data caches
???DDR3 memory interface
???Debug module
???Interrupt controller
???Ethernet controller
???DIP switches, LEDs and push button interface
???SPI flash interface
???Clock generator and system reset logic

The LEON3 is a synthesisable VHDL model of a 32bit processor compliant with the SPARC V8 architecture developed by Aeroflex Gaisler AB in Sweden. The model is highly configurable and particularly suitable for system-on-a-chip (SOC) designs. The full source code is available under the GNU GPL licence, allowing free and unlimited use for research and education.

1???2???3?Next Page?Last Page

Article Comments - Examine soft-core processors for emb...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top