Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > FPGAs/PLDs

Examine soft-core processors for embedded systems

Posted: 21 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:microprocessor? embedded system? FPGA? microcontroller?

The LEON project was started by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects. The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost.

???No licences are required for research and education use.
???All RTL source code is available
???Fast support
???Linux and RTOS can be installed

???Not all FPGA development boards are supported.
???Not in widespread use

The complete design environment for the LEON3, including all the IP cores, can be downloaded from the Gaisler Aeroflex webpage ( The AMBA-2.0 AHB/APB bus has been selected as the common on-chip bus due to its market dominance (ARM processors) and because it is well documented and can be used for free without licence restrictions. The LEON3 can be easily configured using a graphical user interface.

The MicroBlaze
The 32bit MicroBlaze soft processor core from Xilinx is a classic RISC architecture. It was originally developed around the end of 2000 and the beginning of 2001, and it was released later that year. Thereafter, the MicroBlaze has continued to evolve with new functions being added on a regular basis. For example, the most recent release, version 8.20, is equipped with the new AXI bus interface.

???Can be used in all Xilinx FPGA families
???Lots of configuration options
???Uses the AXI standard bus

???Can be used only in Xilinx FPGAs
???EDK needs a licence
???Source code not available
???Xilinx Linux support is very basic (this may change now that they have bought PetaLogix)

The MicroBlaze soft-core processor is fully integrated in the Xilinx FPGA design environment. It can easily be configured for many different applications from a simple controller to a fully-fledged Linux processor. The Xilinx EDK environment makes it very easy to configure the processor and add all the peripherals needed to build a complete processor system.

The OpenRISC
The OpenRISC project was started in 1999 by a group of Slovenian university students. Their aim was to create an open source microprocessor architecture specification and implementation. Two years later, they had produced a complete architectural specification, architectural simulator, and Verilog HDL implementation and made everything publicly available through their new open hardware community, OpenCores.

The OpenRISC 1200 (OR2100) is a synthesisable CPU core maintained by the developers at The OR1200 design is an open source implementation of the OpenRISC 1000 RISC architecture. The Verilog RTL description is released under the GNU Lesser General Public License (LGPL).

?First Page?Previous Page 1???2???3?Next Page?Last Page

Article Comments - Examine soft-core processors for emb...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top