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Reduce power estimation time from weeks to hours

Posted: 25 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:gate-level waveform? RTL? VLSI?

In this article, we will look into a new methodology that automatically generates a chip design's gate-level waveform from the RTL design environment without the need to bring up the gate-level environment. The new waveform generation methodology reduces the effort to perform gate-level power estimation from weeks to hours, using EDA technology from Springsoft and Cambridge Silicon Radio's power estimation flow and tools. This major reduction in effort and increase in designer productivity enables CSR to analyse power characteristics much earlier in the design flow than is practically possible using traditional, high-effort gate-level analysis. Moreover, the new methodology produces waveforms identical (or nearly identical) to those generated by gate-level simulation. Consequently, the design can be analysed and optimised iteratively throughout the post-synthesis design flow, enabling much earlier detection and easier resolution of power issues. The paper discusses:

???Power analysis challenge
???New automated gate-level waveform methodology
???Springsoft's Siloti Visibility Automation System
???Analysis results

Power analysis challenge
One approach to reducing power analysis effort is to perform it at the register transfer level (RTL). Although faster and easier than gate-level analysis, its accuracy is limited to about 20 to 25 per cent because synthesis/place and route are subject to many variables. These variables include the synthesiser's various approaches to meeting timing constraints, as well as its RTL implementation choices, for example, the use of special cells or clock tree insertion techniques. Consequently, RTL analysis is inadequate for the fine-tuning necessary to achieve the low power goals of a complex VLSI design. It is suitable for comparing the power characteristics of design revisions and tracking trends. However, it is certainly not accurate enough to sign-off the design to production, especially a design that must meet a stringent power specification.

There are several approaches to estimating power consumption accurately. One of the common approaches is to estimate it on the post-place and route netlist using full annotation generated from simulation of real scenarios on the same netlist, with or without the standard delay format (SDF). In this approach all the clock tree and all the wire capacitance are taking into account in the most accurate way. This approach necessitates bringing up the gate-level design environment.

Gate-level waveform generation challenge
Generating a gate-level simulation environment is a very high effort task because of naming mismatches between synthesis and simulation. Synthesis is often performed at a different RTL interface than that used by simulation. Since signal names are not maintained during synthesis, the process of matching the new interface to the previous interface is a tedious, time-consuming manual task. Moreover, after place and route, the interface can change completely, making the task even harder.

In addition, this traditional approach produces a waveform that always requires simulation to be run from time zero. This not only results in long simulation run times; it also makes it necessary for the design team to locate cycles that are relevant to the power estimation task. Given that gate transfer level (GTL) waveform files are large and complex, manually locating the relevant cycles is very time-consuming.

Because of the long simulation runtimes, the considerable effort to match and debug the naming, and the effort required to locate power-relevant simulation cycles, many design teams perform gate-level simulation only at the final stage of the project. This is far too late in the flow to optimise power effectively and efficiently. Indeed, many design teams abandon power analysis before its completionthey simply run out of time.

New automated gate-level waveform generation methodology
The new methodology developed jointly by CSR and SpringSoft:

???Generates accurate gate-level waveforms automatically;
???Enables design teams to correlate and analyse results in the RTL environment, eliminating the necessity to bring up the gate-level environment;
???Eliminates the necessity to simulate from time zero for every power analysis run; and
???Imposes no changes on the established power estimation methodology and tool flow.
It combines Springsoft's established Siloti Visibility Automation System with CSR-generated map files that use CSR scripts on regular synthesis and place and route tools. Like some emulation and FPGA design tools, the visibility automation system can extract full waveforms from essential signal waveforms (flip-flops and input). In addition, it maps every gate-level flip-flop to the original flip-flop in the RTL. The combination of these features is used to extract the essential signals from the RTL. The result is a gate-level waveform that is identical (or almost identical) to the GTL waveform derived from GTL simulation. Thus, it can be used to derive the toggle rate of every port of every cell in the netlistprecisely the data needed for accurate power estimation.

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