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Arasan rolls out NAND controller IP, PHY sol'n

Posted: 21 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:NAND flash controller? IP core? NV-DDR2?

Arasan Chip Systems Inc. has uncloaked what it touts as the most complete solution of ONFI 3.1 NAND controller IP & PHY, including ONFI 3.1 compatible NV-DDR2 I/O pads. The company has ported its ONFI 3.1 NV-DDR2 I/O pads in to advanced process running at 400MT/s with 200Mhz clock, Arasan indicated.

Focusing on high performance and high reliability, Arasan's ONFI 3.1 NAND flash controller IP claims to offer a high performance digital controller IP core with soft PHY and the hardened ONFI 3.1 compatible I/O pads supporting 1.8V and 3.3V operation. Compliant to the ONFI 3.1 electrical interface, Arasan's IP core solution, delivered in RTL including synthesisable DLL and PLL, supports NV-DDR2 up to the specification's full 400MT/s. The ONFI 3.1 compatible I/O pads support 200Mhz NV-DDR2 operation at 1.8V. These pads differ from typical high speed DDR I/O pads in that they also support 3.3V I/O operation to enable backward compatibility with ONFI 2.x. The combined controller IP with soft PHY and the I/O pads accelerates time-to-market by reducing SoC designers' development time otherwise spent on ensuring high speed signal integrity, noted the company.

Optionally, Arasan also provides a hardened ONFI 3.1 PHY delivered in GDSII including DLL and PLL. It includes the I/O pads compatible to ONFI 3.1 high speed operation at 1.8V or 3.3V. To support DDR running at 200Mhz to achieve 400MT/s, or 2.5ns window for sampling data, the DLL and PLL become the critical elements to accurately control the sampling clock and the control signals to avoid possible timing variations resulting from extreme temperature, supply voltage and manufacturing process variations. By using Arasan's hardened ONFI 3.1 PHY solution with its proven DLL and PLL, SoC designers can now confidently and easily integrate the ONFI 3.1 PHY into their SoC using Arasan's proven solution, the company added.

Arasan's ONFI 3.1 NAND controller IP supports SLC, MLC and TLC NAND Flash up to 128Gb, synchronous and asynchronous NAND interfaces, page size up to 16KB, BCH ECC engine correcting 32bit or more errors, and eight chip-selects. When integrated in a SoC, Arasan's ONFI 3.1 NAND flash controller IP also supports a variety of host bus interfaces for easy adoption into any system architecture with AMBA3-AXI/AHB/APB, OCP or other custom buses. Arasan also provides ONFI 3.1 software stack and driver for system to facilitate and reduce the product development time.

Arasan's ONFI 3.1 NAND Controller Total Solution including Controller IP core with DLL & PLL delivered in RTL, ONFI 3.1 I/O pads delivered in GDSII, and the optional ONFI 3.1 PHY with DLL & PLL delivered in GDSII are available for shipment.

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