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Imec, Cadence team up for DFT solution for 3D memory

Posted: 24 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:test logic-memory interconnects? DRAM-on-logic stacks? Wide-I/O mobile? design-for-test? ATPG approach?

Nano-electronics research institute imec, has recently announced that it has teamed up with Cadence Design Systems to develop, implement and validate an automated 3D Design-for-Test (DFT) solution to test logic-memory interconnects in DRAM-on-logic stacks. Based on Cadence Encounter technology, the solution was verified on an industrial test chip containing a logic dia and JEDEC-compliant Wide-I/O Mobile Dram.

Memory-on-logic 3D stacks offer the possibility of heterogeneous integration with dense low-power inter-die interconnects. Hence, they are amongst the first 3D products that will come on the market, enabling next-generation high-performance low-power mobile applications.

Recently, JEDEC has released a standard (JESD-229) for stackable Wide-I/O mobile dynamic random access memories (DRAMs) specifying the logic-memory interface. Unlike many previous DRAMs, the standard contains boundary scan features to facilitate interconnect testing. Imec and Cadence now present a design-for-test (DFT) architecture and corresponding automatic test pattern generation (ATPG) approach. It is an extension of their previously announced logic-on-logic 3D DFT architecture and it supports post-bond testing of the interconnects between the logic die and the DRAM stacked on top of it.

The solution implemented by Cadence and imec includes the generation of DRAM test control signals in the logic die and the inclusion of the DRAM boundary scan registers in the serial and parallel test access mechanisms (TAMs) of the 3D test architecture. The automated design for test solution has been validated on an industrial test chip. The design of the test chip is an interposer-based 3D stacked IC which includes a silicon interposer base die, a 94mm2 logic system-on-chip in 40nm technology, and a single Wide-I/O DRAM rank. The validation results show that the silicon area of the additional DFT wrapper is negligible compared to the total logic die size (Part of the work has been performed in the project ESiP, which is co-funded by the ENIAC Joint Undertaking.





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