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ASIC prototyping platform ready for design partitioning

Posted: 25 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? ASIC gates? SoC? ChipScope Pro? LVDS interconnection?

SoC solutions provider S2C Inc. has recently debut its latest prototyping platform, the Quad V7, to its V7 TAI Logic Module series, a new generation of SoC/ASIC prototyping hardware based on Xilinx's Virtex-7 2000T All Programmable 3D ICs.

S2C's V7 TAI Logic Module series use up to 9 Virtex-7 2000T devices on a single board to make SoC/ASIC prototyping a productive experience for designs of any size from 20 million up to 180 million ASIC gates. S2C has integrated Xilinx's Vivado Design Suite in its prototype creation software flow and ChipScope Pro tools in its debug software for accelerated design productivity. In addition, the Quad V7 TAI Logic Module hardware is designed to run high-frequency pin-multiplexing through LVDS interconnection bus to fit designs when partitioned to multiple FPGAs.

"Xilinx's Virtex-7 2000T All Programmable 3D ICs with their Stacked Silicon Interconnect (SSI) technology are changing the landscape of SoC/ASIC prototyping by enabling advanced system integration capabilities. SSI technology allows multiple die to be combined in a single package to deliver almost 3 times more logic, memory, serial transceivers, and processing elements than previously available FPGAs," noted Mon-Ren Chene, Chairman and CTO of S2C.

Rapid FPGA-based prototyping has become a critical step for a successful SoC product launch but was not a viable option when design sizes were extremely large. With four Virtex-7 2000T All Programmable 3D ICs on a single SoC/ASIC prototyping platform, designers can now fit a fairly large design such as an SoC with multi ARM-A15 Cores and multi GPU cores. Traditionally, complex SoC verification has been performed by using expensive emulators that run only at a small fraction of real clock speed, making software development painful.

"S2C's Quad V7 TAI Logic Modules now allows designers to deploy multiple SoC/ASIC prototypes for both hardware verification and early software development, so the overall SoC design cycle can be greatly reduced. On the technical aspect, we have designed the interconnections between the 4 All Programmable devices to run large number of LVDS pairs synchronously at over 800MHz. With dedicated LVDS Pin-Multiplexing reference clocks and reset circuits, almost any design can be partitioned easily to our Quad V7 TAI Logic Module."

S2C also provides optional prototype creation and multi-FPGA debug software; DPI, SCE-MI and C-API co-modeling; and, a large library of off-the-shelf Prototype Ready IP & Accessories to speed up the creation of design prototypes using the V7 TAI Logic Modules.

The Quad TAI Logic Module is available now. The Single and Dual V7 TAI Logic Modules have been shipping since June 2012. The Nine TAI Logic Module is scheduled to release in Q2 of 2013.





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