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Phoenix-RTOS gets ported to eSi-RISC processors

Posted: 29 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:M2M communication? smart grid? embedded systems?

EnSilica and Phoenix Systems have ported the Phoenix-RTOS, geared for both single and multi-core embedded systems applications, to the eSi-RISC family of highly configurable soft processor cores. According to the firms, their team up expands the eSi-RISC ecosystem with an embedded RTOS that can use eSi-RISC's hardware MMU with memory protection and security features such as data execution protection.

The initiative, likewise, paves the way for embedded power line and wireless smart grid solutions with the combination of Phoenix Systems' proposed smart grid software protocol stacks and eSi-RISC's support for custom instructions accelerating performance and improving PHY layer implementations, added the companies.

The Phoenix-RTOS boasts modularity and portability, coupled with a small footprint, virtual memory support and an advanced architecture that implements the latest OS mechanisms and programming abstractions, said the companies. The fully re-entrant and pre-emptive kernel supports scheduling strategies that allow for the prioritisation of critical task execution. Additional components, such as TCP/IP and USB stacks, common file systems and POSIX interface, further leverage its potential for M2M communication and smart grid applications, the firms indicated.

EnSilica's eSi-RISC family claims to provide a range of high quality, highly configurable embedded processors that are easy to integrate. The processor sub-system is delivered fully targeted to customers' ASIC technology, thereby reducing integration effort. eSi-RISC processors provide the flexibility to define a range of hardware functions to optimise the silicon area, the firms stated. OnCchip memory requirements are reduced through inter-mixed 16bit and 32bit instructions, resulting in good code density without compromising performance. The incorporation of a hardware MMU coupled with multiple execution privilege levels enable critical applications to be run separately to ensure they don't interfere with one another.

eSi-RISC is the only processor family scalable from 16bits to 32bits, starting from as low as 8.5k gates, the companies stated. It uses the industry standard GNU optimising C/C++ compiler and Eclipse IDE for rapid software development, and supports efficient debugging on the target through a JTAG interface and hardware breakpoints. The development suite, which will include Phoenix-RTOS in the next release, is common to both 16bit and 32bit processors, protecting users' software investment, concluded the companies.

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