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Open ecosystem team up spawns 3D IC

Posted: 31 Jan 2013 ?? ?Print Version ?Bookmark and Share

Keywords:memory test chip? TSV? package-level reliability? FEOL? 3D chip stack?

STATS ChipPAC Ltd. and United Microelectronics Corp. (UMC) have demonstrated what they say is the world's TSV-enabled 3D IC chip stacking technology developed under an open ecosystem partnership. The 3D chip stack, which consists of a Wide I/O memory test chip stacked upon a TSV-embedded 28nm processor test chip, reached a major milestone on package-level reliability assessment, added the companies.

"The next level of chip integration is rapidly evolving, and 3D IC technology is poised to enable the next frontier of IC capabilities for customers under various deployment models." said Shim Il Kwon, VP of technology innovation of STATS ChipPAC. "The open ecosystem collaborative approach drives proven and reliable 3D IC solutions for the semiconductor market by combining the foundry partner's robust, leading-edge TSV and front-end-of-line (FEOL) process technologies in a complementary platform with an Outsourced Semiconductor Assembly and Test (OSAT) service provider with innovative engineering excellence to seamlessly integrate mid-end-of-line (MEOL) and back-end-of-line (BEOL) 3D IC processes."

S.C. Chien, VP of advanced technology development at UMC, said, "We see no imperative to restrict 3D IC to a captive business model, as UMC's development work with nearly all the major OSAT partners for 3D IC has been very productive. Our successful collaboration with a leading OSAT partner like STATS ChipPAC has further established the viability of an open ecosystem approach."

UMC and STATS ChipPAC's proven open ecosystem 3D IC approach sets an important standard for collaboration within the industry supply chain to achieve mutual success, they claimed. Under the 3DIC open development project with STATS ChipPAC, UMC provides the FEOL wafer manufacturing, with a foundry grade fine pitch, high density TSV process that can be seamlessly integrated with UMC's 28nm poly SiON process flow. The know-how developed will be applied towards implementation on the foundry's 28nm High-K/metal gate process. For MEOL and BEOL, STATS ChipPAC performs the wafer thinning, wafer backside integration, fine pitch copper pillar bump and precision chip-to-chip 3D stacking.





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