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Nvdia exec to tackle challenges of chip design in keynote

Posted: 05 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:GPU engineering? Moore's law? EDA companies? chip design? FinFETs?

Chip design has become increasingly complex. Moore's law has been a relentless taskmaster, raising the bar for chip designers and manufacturers on a yearly basis with no let-up. A single mistake and a firm would have suffered a major setback, taken by surprise for not clearly anticipating the changes expected in the next generations of chip design.

This year at DesignCon, senior vice president of GPU engineering at Nvidia, Jonah Alben, is set to deliver a keynote speech on the challenges associated with delivering successful chip designs, while sharing the firm's experiences regarding investments in tools and methodologies, including recent success with GPU-accelerated simulation software.

"All chip developers are interested in methodology improvement," said Alben. "The hard part is putting the right level of investment in place when project execution always needs more people."

Alben said he planned to draw on those experiencesdesigning GPUs at Nvidiato illustrate some of the ways in which the firm had tackled those problems to date.

Alben, who now leads the development of next-generation GPU architectures, joined Nvidia back in 1997 as an ASIC design engineer and worked his way up. Along the way he managed to pick up no less than 34 patents.

As part of his current role, Alben and his team work directly with EDA companies to apply the parallel computing horsepower of GPUs to the chip development process.

"As chips get bigger and more complex, while CPU performance scales very slowly, generating simulation results quickly is increasingly difficult," he said, noting that with GPU computing, the firm found it was able to dramatically accelerate the feedback loop.

Analyst David Kanter from Real World Technologies said that to his mind, power management and keeping cost under control for newer process technologies still represented the biggest challenges.

"New techniques like High-k/metal gates, FinFETs, etc. are resulting in higher foundry pricing. So leading edge applications like GPUs and FPGAs must be able to deliver end-user value to justify the highest costs," he said.

There's no question that it is much harder as a fabless company, because co-design is limited.

"Foundries have to develop a leading process which is attractive to the likes of Qualcomm and Nvidia today, but will be efficient for the broader market in the future," said Kanter.

By the same token, however, being an integrated device manufacturer (IDM) requires more and more revenue.

"I think the key challenge for fabless companies is to strengthen their physical design and work more closely with foundries," said Kanter, noting that while it used to be true that being fabless meant you didn't worry about process technology, that simply wasn't possible anymore today.

"I think the challenge is figuring out how to get some of the benefits of an IDM model, but without actually owning the fab and doing the process technology R&D," he concluded

- Sylvie Barak
??EE Times

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