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DCD outs LIN IP core

Posted: 05 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Local Interconnect Network IP core? DLIN? CAN? LIN?

Digital Core Design (DCD) has unleashed a Local Interconnect Network IP core that is compatible with the LIN 1.3, 2.1 and the newest version 2.2 Revision A,�released by the LIN Consortium. According to the company, DLIN is described at RTL level, empowering the target use in�both, FPGA and ASIC technologies, and is touted as a solution for automotive designs.

Compared to the CAN, LIN is slower, but thanks to its simplicity, it is much more cost effective, boasted the company. That's why the DLIN is geared for communication in intelligent sensors and actuators, where the bandwidth and versatility of CAN is not required. DCD's IP core provides an interface between�a microprocessor/microcontroller and a LIN bus. It can work as a master or as a slave LIN node, depending on a working mode determined by the microprocessor/microcontroller.

The reported information status includes the type and condition of transfer operations being performed by the DLIN, as well as a wide range of LIN error conditions (overrun, framing, parity, timeout). DCD's IP core includes also a programmable timer, which allows to�detect timeout and synchronisation error.

DLIN features automatic LIN header handling and re-synchronisation, and data rate between 1Kb/s and 20Kb/s. Available system interface wrappers include AMBAAPB Bus, Altera Avalon Bus and

Xilinx OPB Bus.

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