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UMC, Synopsys partner for design verification at 28nm

Posted: 12 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:design verification? IC Validator? IC Compiler? DRC?

United Microelectronics Corp. (UMC) has selected Synopsys' IC Validator physical verification product for lithography hot-spot checking at the 28nm process node. UMC standardised on IC Validator pattern matching, a patented technology enabling ultra-fast detection of manufacturing-limiting layouts, which can dramatically accelerate final design signoff, the companies indicated.

As part of Synopsys' Galaxy Implementation Platform, IC Validator is an ideal add-on to Synopsys' IC Compiler solution for In-Design physical verification, enabling place-and-route engineers to accelerate time to tape-out by preventing late-stage surprises and minimising manual fixes, said the firms. IC Validator pattern matching extends the In-Design flow with automatic repair of lithography violations, further optimising design turnaround time.

Achieving lithographic printability at 28nm and below can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. IC Validator simplifies this task with innovative, patented pattern-matching technology, which augments traditional DRC with intuitive 2D multi-shape pattern-based analysis. Pattern matching enables foundry-quality accuracy and ultra-fast performance, helping to detect lithography hot-spots significantly faster and improve time-to-tape-out.

IC Validator pattern matching extends the benefits of In-Design physical verification with IC Compiler to eliminate late-stage surprises and manual fixes. With pattern matching, designers are now able to screen for lithography hotspots in a push-button manner, right within the implementation environment. Fast pattern-matching analysis uses the entire In-Design infrastructure, including intuitive error reporting, GDS merging, error categorisation and more. Once detected, violations can be automatically repaired during routing, saving many hours in tedious and error-prone manual fixes. In-Design physical verification with pattern matching makes it possible for designers to reach and maintain a healthy design earlier, resulting in improved final layout quality and further eliminating accumulation of schedule risk.

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