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Circuit simulator eases memory design verification

Posted: 13 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:memory design? circuit simulator? FastSPICE? SPICE?

Synopsys Inc. has released the 2012.12 version of its FineSim circuit simulator. According to the company, the solution introduces new algorithms for layout resistance and capacitance (RC) parasitic reduction and complex on-chip power network simulation, enabling up to twice simulation speed-up and capacity for post-layout simulation of various memory designs compared to previous versions of FineSim.

In addition, this release of FineSim incorporates the industry-proven HSPICE device modelling engine, which includes support for the FinFET BSIM-CMG 106.1 standard. The company added that the built-in HSPICE modelling engine ensures that FineSim simulation results are consistent with HSPICE golden accuracy simulations.

Synopsys' FineSim solution claims to offer a unique high-performance circuit simulation technology that combines FastSPICE and SPICE simulation in a single executable, enabling designers to seamlessly switch between FastSPICE and SPICE simulation with no netlist reformatting or environment changes. This unique capability provides maximum flexibility and ease-of-use for circuit designers, enabling them to take advantage of FastSPICE performance when the highest throughput is needed and switch to SPICE mode when the highest simulation accuracy is critical.





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