Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > EDA/IP
?
?
EDA/IP??

Paper tackles 3D IC temperature solutions

Posted: 19 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:3D? TSVs? PCB? thermal environment?

In designing 3D integrated circuits (IC), multiple chips in a package are often stacked up closely through connections of TSVs and micro-bumps. These versatile connections allow more functionality to be compressed into a small footprint for chips targeting low-power mobile, high performance computing, and consumer and automotive electronics.

A key challenge with 3D IC system environments is thermal interactions and thermal-induced stress failures because of the higher temperatures and complex thermal distribution. For instance, temperature profiles on a 3D IC are the result of thermal interactions with other chips, thermal conductive paths in a package, the PCB the package is mounted on that has other heating components, multiple PCBs, airflows and radiations inside the box, and the thermal environment outside the box.

To solve the temperature challenges of 3D IC or silicon interposer-based designs with TSVs requires using advanced modelling, simulation and debug capabilities that includes a detailed chip power map of the device and metal layers in order to achieve accurate thermal distribution and incorporating system thermal simulation in the power-thermal loop.

In a paper entitled Thermal Co-analysis of 3D IC/Packages/System, co-founder of Apache Design Solutions Norman Chang features real case studies of temperature solutions for chips, thermal back-annotation for chip reliability and performance, system impact on chip temperatures, and transient responses of power mode changes in 3D ICs using ANSYS-Apache technology.

The methodology flow presented in the paper will demonstrate the link between the 3-D IC package thermal simulation with the system (PCB/box) thermal simulation through the exchange of power maps per die and thermal boundary conditions that will enable chip-package-system design sign-off on thermal/stress aspects and provide an accurate thermal chip solution.

- Nicolas Mokhoff
??EE Times





Article Comments - Paper tackles 3D IC temperature solu...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top