Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > Memory/Storage

Memory test tip: Boost flash memory testing

Posted: 25 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Source measurement unit? non-volatile memory? NAND?

To program or erase a flash memory cell, a set of pulses are applied. Pulses are used because applying a steady DC voltage would cause the cell to be over programmed or over erased, which typically damages the gate oxide so that the cell cannot be set to the opposite state. The stimulus voltage must be applied in a time-controlled manner, which is why a pulse generator is required.

Using pulse generators
Typical applications for pulse generators include preventing device heating, exposing devices to time-controlled stressing or charging, generating clock signals, testing fuses, and setting and resetting memory devices. A pulse generator can output a voltage in a time-controlled, time-accurate manner, allowing the user to tailor the amount of voltage (pulse height) and the duration of the pulse (pulse width), as well as the voltage ramp rate (rise and fall time). This type of instrument also provides the ability to control the number of pulses output and even to synchronise multiple pulses. Fortunately for memory device manufacturers, a growing number of parametric test systems offer pulse generators as optional equipment.

Figure 3: A single-bit cell (top), which can be in one of two states, requires two distinct voltage levels VT for set or reset. Multi-bit cells (bottom) can be in one of four to eight states, requiring a pulse generator that can generate four to eight values of VT.

NAND flash cells fall into two categories: single bit (logical 0/1) and multi bit. As the names imply, in a single-bit cell, each storage location can hold only one bit; in a multi-bit cell, each storage location can hold multiple bits. Single-bit cells require a two-level pulse to set or reset the device, which results in two distinct VT values (figure 3). Multi-bit cells need multi-level pulses to place the cell in each of its possible states, which requires pulses with from four to eight possible voltage levels.

To program a single-bit cell using FN tunnelling, a positive pulse is applied to the gate, while the drain, source, and bulk voltages are set to 0 V (grounded). This causes charge to be pushed into the floating gate. To erase the cell via FN tunnelling, a negative pulse is applied to the gate (drain, source, and bulk terminals set to 0 V or connected to ground).

To program the cell using HCI, simultaneous pulses are applied to the gate and drain (source and bulk grounded or set to zero). This causes a field to appear in the transistor channel, thereby creating the necessary hot carriers. The pulse height and polarity of the gate pulse determine whether charge is applied to or removed from the floating gate.

?First Page?Previous Page 1???2???3?Next Page?Last Page

Article Comments - Memory test tip: Boost flash memory ...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top