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Implement analogue functions in rugged FPGAs

Posted: 26 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? DC/DC converters? ADC? DAC?

FPGAs have already altered the cost/reliability paradigm for embedded systems in high-reliability applications, thanks to advances in hardness and power reduction. However, on many embedded applications for high-reliability markets, designers depend on a number of peripheral analogue components such as analogue-to-digital and digital-to-analogue converters to talk to the real world. Other system components such as phase-locked loops (PLLs) and DC/DC converters are usually required to complete a system design. These peripherals impact overall cost, size and reliability. Peripheral analogue parts can also be challenging to work with and to source for radiation environments, as an example.

To further leverage the power of FPGAs, military-and-aerospace engineers are actively looking for ways to integrate many of these analogue functions onto the FPGA. Synthesisable, digital IP cores that replace some analogue functions now exist, allowing mil/aero designers to implement ADC, DAC, DC/DC controller and clock-multiplier functions in fully digital processes such as FPGAs. Not only does this new ability leverage the advantages of FPGAs, it also helps mitigate many challenges of using analogue components in high-reliability applications.

Overcoming high-reliability design challenges
The engineering challenges of designing for military or high-reliability applications such as aerospace are numerous. Power and weight are usually under strict budgets because they can affect operating costs and insertion costs exponentially. Physical shock safeguards, force survival and protection from single-event upsets (SEUs) and latchup often mean that parts are larger, heavier and more power hungry than commercial devices. For instance, a commercial 12bit, 10MHz bandwidth ADC measures approximately .71 by .42 inch (convert to mm except for displays)es (convert to mm except for displays) and consumes 280 milliwatts. The equivalent radiation-hardened part is .81 by .72 inch (convert to mm except for displays)es (convert to mm except for displays) and consumes 335 mW. That's almost double the size at 20 per cent more power.

A wide temperature range is another issue. Typically, temperatures of -40C to +80C are expected for many military embedded applications here on Earth. Temperature takes on another complexion in space. In satellite electronics design, for instance, the normal operating junction temperature might be -55C to +125C. Monitoring this onboard temperature is key to effective system maintenance, but installing a rad-hard ADC part to provide this function can add up to one square inch of board and require additional components and testing.

When a high-reliability design makes use of peripherals such as ADCs, DACs, DC/DC converters or PLLs, each one of those components represents a possible point of failure. Each must be qualified and tested, and each is most likely not optimally designed for the specific need. There is also always a risk that the manufacturer will discontinue the part, forcing requalification of the entire system.

These challenges to working with analogue components in high-reliability environments can evaporate by using the FPGA for a unified, all-digital approach. Let's take a look at this new paradigm in military/aerospace design.

Pulling analogue functions onto the FPGA
Regardless of how you define "analogue" and "digital," significant differences and integration issues exist between the two. Because of these issues, it can be very advantageous to have digital designers pull analogue functions onto an FPGA and test them. Herein, we will define "digital" as using standard digital library cells and passive components for a fully synthesisable and digitally testable design. Designers can create digital IP blocks of ADCs, DACs, DC/DC converter controllers and clock multipliers in RTL format and implement them in all-digital processes.

With these IP blocks, military designers can take advantage of rugged and radiation-hardened FPGAs to implement customised analogue functions. Not only does this approach leverage the inherent protection properties of the FPGA, but these blocks are also a great way to utilise unused FPGA resources. Xilinx recognises this advantage and now partners with Stellamar to provide these functions. Increasingly, aerospace companies are turning to these solutions to attack analogue-integration problems.

Digital ADC core yields benefits
Figure 1 depicts an example block diagram of a Stellamar Digital ADC IP core. With the digital approach, the core requires only a few external passive components. The IP core is instantiated right inside the FPGA and is easy to implement through digital synthesis. On a Xilinx Virtex-5QV device, a scenario such as that pictured in figure 1 utilises less than 1 per cent of FPGA resources.

Figure 1: An example of a fully digital ADC IP core interface.


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