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Implement analogue functions in rugged FPGAs

Posted: 26 Feb 2013 ?? ?Print Version ?Bookmark and Share

Keywords:FPGAs? DC/DC converters? ADC? DAC?

Proprietary signal processing makes it possible to replicate analogue sigma-delta ADC performance with all-digital library cells. Companies like SEAKR Engineering and the Finnish Meteorological Institute are using Digital ADC IP in their On Board Processor Program and Lunar Landing Missions, respectively. Some touted benefits are:

???50 per cent lower power than analogue ADC parts
???68 per cent smaller area than analogue ADC parts
???Process technology independence
???Reduced risk and cycle time
???Digital integration, synthesis and testing
???Easier radiation-hardened design

Performance plus applications
Current performance is up to 15 bits of resolution and several hundred kilohertz of bandwidth. Bandwidth depends on the selected resolution. This level of performance is suitable for a host of applications including sensors (temperature, pressure, voltage, current and acceleration), touchscreen integration, high-quality voice and motor control.

As an example, many design teams use a radiation-hardened, 12bit, 10MHz bandwidth ADC part for monitoring onboard temperature and voltage. Some FPGAs, such as the Xilinx Virtex-5QV space-grade FPGA, even have embedded diodes highlighting the importance of the temperature-sensing function. However, normal bandwidths for these types of measurements are 0.5Hz to 10Hz, so using bandwidth in the megahertz is like driving the head of a pin with a sledgehammer. A Digital ADC IP core on a radiation-hardened FPGA can get down to 0.5Hz bandwidth per channel and can consume less than 6 mW, compared with 335 mW for the external part. Why waste critical board space and power for such a low-level task?

Controlling DC/DC power management
Power management is becoming a larger part of overall system design. Sometimes a single design can include more than 30 power supplies. External radiation-hardened DC/DC converters retain the same difficulties as external ADCs. Thus, the use of these parts to control power complexity in high-reliability applications does not scale well.

All-digital DC/DC controller IP now exists to take advantage of radiation-hardened FPGAs' processes and to allow for simplification of control, redundant power supplies, infinite sequencing and infinite throttling (figure 2). You will still need an external power transistor, but this can be much easier to work with than a full DC/DC converter part.

Digital clocking solutions
Phase-locked loops are some of the most widely used analogue blocks for clock generation; thus, most FPGAs have incorporated PLL capability within the package. However, some FPGAs, including certain radiation-hardened FPGA families, do not include PLLs at all. Other radiation-hardened FPGAs generally do not include the PLLs in the rad-hard portion of the package.

Digital clock multiplier IP used on these FPGAs can provide the ability to generate any clock up to about 2GHz with no lock time. Models show 50ps peak and 35-ps RMS, with 5-ns to 1-ns rise/fall. As with Digital ADC IP, this solution requires very few off-the-shelf passive components.

Figure 2: Example DC/DC controller block diagram.

Putting it together
Historically, FPGAs did not lend advantages to analogue functions, forcing high-reliability design teams to use non-optimal external analogue parts. This is no longer the case, as mil/aero engineers now have robust options for integrating analogue functions into any digital fabric, including radiation-hardened FPGAs. By using digital implementations of analogue functions from Stellamar, engineers can add critical functionality such as thermal monitoring, redundant power supplies and clocking functionsCall without adding weight, power or size to the design. The digital synthesis and test methodology ensures the operability and greatly increases reliability.

Further, designers can easily leverage these technologies across projects and across the whole organisation. With budgets being slashed and performance more important than ever, these digital IP cores give mil/aero engineering teams the flexibility and productivity they need to meet critical mission objectives.

About the authors
Allan Chin is CEO of Stellamar.

Luciano Zoso is CTO of Stellamar.

To download the PDF version of this article, click here.


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