**Amplifiers/Converters??**

# Understand perfect pseudo-differential input ADCs

**Keywords:pseudo-differential?
filter?
common mode rejection?
**

My first thought was of multiplexed differential inputs where each input signal is measured relative to the same reference signal. In other words, the inverting input of the ADC is constantly connected to this reference, while a single-ended multiplexer feeding the non-inverting input cranks round a set of input signals. Turns out that's not what my colleague was talking about. I have a feeling that such inputs are called quasi-differential 每 quasi, of course, being another of those pseudo-prefixes, this time meaning "almost, having some resemblance to". But the great Richard Feynman was always clear that knowing what people call something tells you next to nothing about what it actually does.

The type of 'pseudo' differential input we're talking about here is where you take a sample of the voltage on one input connection that you think of as the non-inverting input, then a sample from another that you consider to be the inverting input, and then subtract one reading from the other. This gives you an indirect measurement of the difference in voltage between the two inputs. Given only a single-ended measurement channel, this allows you to 'fake' a differential input looking at a floating voltage.

If your signals are static and you can rely on the signal that you're not looking at not moving while your metaphorical back is turned, this can work reasonably well. Pretty obviously, though, if either of those signals are changing with time, you're in trouble. Consider the case in which the two signals are in fact identical. If this input signal is varying with time 每 let's say that it contains some AC line voltage hum 每 then the output word from the ADC will change on each sample, and the calculated difference between successive sample pairs will be non-zero even though you know jolly well that it should be zero, because the two signals are the same.

In藩differential input terms, the pseudo-differential ADC you've made has deteriorating common mode rejection at the input, as the signal frequency rises. For a given frequency, things improve as you sample at a higher rate, because the input signal doesn't move as much from sample to sample. But it's quite possibly not enough to make the technique workable in the presence of significant AC common mode signal. So, it sounds like this is a bit of a rubbish solution to the high-performance differential signal monitoring problem. Unless you're prepared to use a little Filter Wizardry, that is!

We can make use of the 'time realignment' filtering process. We'll see how this can help you make not only a high performance pseudo-differential input ADC, but even a multi-channel quasi-pseudo-differential system!

Let's recap the technique.藩The process starts with the selection of a lowpass FIR filter response that's suitable for use as a decimation filter to reduce the sample rate by a factor equal to the number of channels N being processed. This requires the filter to have a stopband beginning at F_{s}/2N, with Fs being the sample rate that the ADC is taking data at.藩The passband behaviour of our final output channel is going to be determined by the passband properties of this filter, while the attenuation in the stopband is going to determine the ultimate common mode rejection performance. The tap count is chosen to be divisible by N.

Since this starting filter's stopband is positioned to permit subsampling at the output by a factor of N, it follows that any of the N ways of taking every Nth sample is a legitimate decimation-by-N of the filtered signal. So this one filter can be "peeled apart", sequentially assigning its coefficients to the N subfilters. Each of these subfilters is then used to process the corresponding channel at the F_{s}/N rate.

An important consequence is that all N filters can be executed in one go after one sample from each of the N channels has been acquired, and all the filtered outputs are then available simultaneously, to do time-aligned cross-channel calculations.

If successive samples of the same signal are applied to the input of every subfilter 每 in other words, if the ADC input is not multiplexed but is just converting a test signal 每 the variation in group delay through each of these different subfilters exactly compensates for the variation in signal delay caused by the channel's position in the sampling sequence. If all of the outputs are viewed simultaneously on a scope, there will be no delay between the representations of that signal at the output.

Provided the initial filter stopband attenuation is selected to ensure suitably low levels of aliasing, the passband frequency responses of the subfilters will be almost identical. This means that the difference signal obtained by subtracting two channels will be very low not only at DC, but for AC signals over the entire operating frequency range of the system. If a disturbing signal is present either on a common external reference potential or in the processing circuits on the ADC front end, it will be rejected by a predictable amount that is only dependent on the digital filter coefficients and is therefore quite unaffected by component tolerance or environmental factors. Meanwhile, any signal component that's unique to only one of the selected inputs will be represented as expected in that channel's data stream.

What we've done is create common mode rejection 每 suppression of a signal that's common to two or more inputs 每 using purely digital techniques. The stopband rejection of the filter (and therefore the common mode rejection) can, in principle, be increased without limit, and no analogue matching requirements are necessary.

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