Toshiba outs low power tech for embedded SRAM

Toshiba Corp. has uncloaked what it says is a low-power technology for embedded SRAM for smartphones and other mobile devices. According to the company, the technology cuts active and standby power in temperatures ranging from room temperature (RT) to high temperature (HT) by using a bit line power calculator (BLPC) and a digitally controllable retention circuit (DCRC). A prototype has been confirmed to reduce active and standby power consumption at 25°C by 27 per cent and 85 per cent, respectively, highlighted the company.

Longer battery life requires lower power consumption in both high performance and low performance modes (MP3 decoding, background processing, etc.). As low performance applications require only tens of MHz operation, SRAM temperature remains around RT, where active and leakage power consumptions are comparable. Given this, the key issue is to reduce active and standby power from HT to RT.

Toshiba's technology applies a BLPC and DCRC. The BLPC predicts power consumption of bit lines by using replicated bit lines to monitor the frequency of the ring oscillator. It minimises the active power of the SRAM in certain conditions by monitoring the current consumption of the SRAM rest circuits. The DCRC claims to greatly decrease standby power in the retention circuit by periodically activating itself to update the size of the buffer of the retention driver.

Toshiba will continue to develop technologies that contribute to high performance, low power system LSI for mobile products.