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A primer on FRAM (Part 2)

Posted: 04 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:ferroelectric capacitor? FRAM? DRAM?

In part 2 of this article, we discuss the specifics of the read and write process with a particular focus on the requirements placed on the ferroelectric capacitor. Part 1 discusses the basic operating principles of FRAM, including the role played by hysteresis.

At the end of the read operation, the capacitor always points UP so if the datum indicated a DOWN state, it must be re-written (figure 1).[1,2] The fundamental FRAM cell looks very much like a DRAM cell with the addition of an extra line. Unlike DRAM capacitors, which see a monopolar bias voltage on their substrate contact, memory circuits must be able to apply bipolar voltages to that side of a ferroelectric capacitor. Therefore, the local substrate contact of the DRAM capacitor is replaced by a plate line and wife connecting the bottom side of the ferroelectric capacitor to a separate driver circuit.

Figure 1: UP and DOWN bit line voltages during the read operation.

The plate line drives all of the ferroelectric capacitors in a single row in the word-parallel cell (figure 2). The capacitive loading on the plate line can be reduced to a single memory cell using the bit-parallel approach. Given the layout and knowing the amount of charge the capacitor will generate, experienced memory circuit designers can proceed apace. Nevertheless, ferroelectric capacitors do have special properties that must be considered in the design.

Figure 2: The plate line in an FRAM may be run parallel either to the word line or the bit line.

The ferroelectric capacitor will generate four to five times more charge than a DRAM capacitor during the read operation. Typically, a DRAM capacitor has a capacitance of approximately 20 fF and a voltage of ? Vcc across it, yielding at most approximately 30 fC stored in a cell of 0.01 to 0.02?m2. A typical ferroelectric capacitor in a commercial FRAM has an area of approximately 0.4?m2 but delivers 32?C/cm2 of polarisation onto the bit line, equivalent to 128 fC of charge. The memory circuit must be able to support the movement of that much charge in the nanoseconds allotted for establishing the bit line sense voltage before the sense amplifier is enabled. The fundamental difference is that where a DRAM capacitor naturally shares its charge with the bit line when its pass gate is enabled, the charge inside the ferroelectric capacitor must be forced from the capacitor by the application of an external voltage from the plate line. The impedance of the drive and sense circuitry becomes the critical limitation, slowing memory cell operation below the maximum speed of the ferroelectric capacitor. Paul Larsen of the Philips Research Laboratory demonstrated in 1992 that PZT could switch as fast as 360 ps.[3] PZT in reality is probably faster.

Bit line capacitance ratio
The voltage generated on the bit line by the two memory states of the ferroelectric capacitor is determined by the capacitance of the bit line relative to the area of the ferroelectric capacitor. This relationship is the bit-line-to-capacitance (BLC) ratio. Equivalent capacitances for the two memory states of the ferroelectric capacitor may be calculated by dividing the expected charge per state by the read voltage. Assuming 10?C/cm2 and 50?C/cm2 for the two states at 2 V for a 0.4?m2 capacitor, the equivalent capacitances are 20 fF and 100 fF. The sense voltages and their differential are then set by adjusting the length of the bit line. Once the bit line length is set, the addition of the sense amps, line drivers, and address decode sets the size of the die.

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