Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
EE Times-Asia > EDA/IP

Issues in using 3rd party IP in ASIC/SoC design

Posted: 15 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:3<sup>rd</sup> party IP? fab-lite? design-lite?

3rd party IP has become a buzz word since the semiconductor industry transitioned to fab-lite and, eventually to, design-lite models over the last few years. These new business models have opened the doors for many companies to overcome some of the internal weaknesses associated with possessing IPs/design competencies to do next-generation ASIC/SoC designs. There have been multiple debates about how, and to what extent, a company should pursue 3rd party IP. This article will outline some of the best practices for using the ecosystem as well as some of the common challenges in integrating and using 3rd party IPs in today's high-end ASIC/SoCs.

3rd party IP market
The strategy of using the 3rd party IP ecosystem has been very successful when one considers the advantages of licensing the IP from the outside world:

Better time-to-market: Using readily available IP can help kick start the chip design and will ultimately lead to shorter design cycles.

???Lower cost: Applying generic foundation IP, like standard cells, general purpose I/O libraries and memory compilers, will often be cheaper when compared to the costs associated with internal IP development, verification and (test-chip) characterization.
???Increased focus: Companies can focus their R&D efforts on their differentiating technology, rather than spending their resources on designing IP, which is often standards-based and provides minimal differentiation to the end product.
???Reduced risk: IP vendors are likely to be early adopters of newer technologies and typically qualify the IP on their own test chip or in collaboration with a lead customer.
Of course, one can argue that this approach has some disadvantages as well:

???Specification compromise: "Off-the-shelf" open-market IP can never be fully optimized for all possible product applications. This provides a major challenge when criteria such as area, performance and features may need to be traded off against aspects like cost, risk and time-to-market. Sometimes an in-between solution, where available IP is customized by the vendor toward the customer-specific application, can make sense.
???No ownership of IP: IP licenses come with various restrictions, which can "get in the way." Examples include: re-use and disclosure and modification rights limitations, which can possibly impair a company's flexibility if not taken into account well in advance.
Looking at both the pros and cons, it probably makes the most sense for a system company to focus only on the development of IPs in-house, which differentiates a product rather than doing all IP development on its own. For example, for a baseband chip, it's imperative to do the processor architecture and hardening, RF system, power management blocks, etc., in house. This will enable the company to differentiate their products from their competitors in the market rather than spending effort on generic IPs like USB, MIPI, HDMI interfaces, libraries, GPIOs, etc., which are easily available in the outside world and probably already silicon proven on the IP vendors' test chip.

Integration of 3rd party IP
Procuring IP from third-party IP vendors looks to be a good option, but selecting and integrating that IP is rapidly becoming one of the biggest challenges in the SoC/ASIC industry. The success of any design depends on the careful selection of a reliable IP which sufficiently meets the product's requirements. Today, a significant portion of metal re-spins or redesign of chips is due to the fact that the IP is not properly selected, it has a bug inside, or it is not properly integrated into the design.

It is very common for IP to be procured from multiple vendors for a single design. Working with each vendor requires careful management of technical, quality, business and legal issues. Taking hard-IP as an example, modern SoCs often integrate multiple high-speed serial interfaces, such as PCIe, USB, and XAUI; memory interfaces such as DDR; CPUs such as ARM, MIPS, and Tensilica; analog IP, including ADCs, DACs, PLLs, DLLs; and power management blocks, next to library and commodity IP that includes memories, I/Os, and standard cells.

Figure 1: Typical SoC components.

1???2???3?Next Page?Last Page

Article Comments - Issues in using 3rd party IP in ASIC...
*? You can enter [0] more charecters.
*Verify code:


Visit Asia Webinars to learn about the latest in technology and get practical design tips.

Back to Top