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Issues in using 3rd party IP in ASIC/SoC design

Posted: 15 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:3<sup>rd</sup> party IP? fab-lite? design-lite?

For each component in a SoC, there are specialized IP vendors with proven track records providing the IP in the whole ecosystem. Though there are many benefits to having multiple sources in the market, it presents challenges for IP integration. To combat this, an IP selection and qualification process is needed. This process needs to be exhaustive and comprehensive while covering each phase of the ASIC design, from specification to GDSII.

Even a small oversight, such as realizing late in the tapeout phase that one of the IPs uses LVt devices, when only RVt/HVt devices have been budgeted for, can have a major impact on cost and schedule. A seemingly small mistake made in the due-diligence stage as performed early in the ASIC development cycle, can lead to excessive costs down the road when the issue is encountered.

Figure 2: 3rd party IP use process.

Figure 2 shows a comprehensive 4-stage IP Selection, Procurement, Qualification and Integration process, starting from day one when the project is still in the specification phase. Understanding customer requirements (or sometimes even driving them), selecting the right vendors, the right IP, conducting IP risk assessment and mitigation, as well as performing qualification and integration checks, are integral parts of any project. Each of these steps is composed of various checks and analysis in order to assure one thing: The right IP is being used in the right manner!

Each part of the 3rd Party IP Use Process seen above is quite rigorous and requires a great amount of effort by the IP procurement and integration team.

Selection, procurement and integration
The IP and Vendor Selection process is the most important step as it is the foundation for the whole design. Taking shortcuts during this process will no doubt increase the chance of failures at later stages. This process encompasses matching the IP requirements as per the design needs, finding the right vendors and making sure that the 3rd party IP serves all the needs required for the particular design.

Also, for the various IP being procured, both compatibility and interoperability need to be insured. For example, in TSMC's 40G process, multiple voltages can be supported for the I/O oxide (1.8, 2.5 and 3.3V). However, not all combinations are supported at this technology node. The selection of different I/O libraries and PHYs needs to take this into account to ensure compatibility of the selected IP. Another example involves DDR PHYs and the associated controllers. Interoperability concerns can exist, especially in cases where the DDR and the PHY are procured from different vendors, as the standard for the interface between them is new and may, to a large extent, still be unproven.

Figure 3: IP aggregation in a design.

IP Procurement is the next important step after all the IP and vendors have been finalized for a design. This process includes financial, legal, schedule and various other contracts/agreements and negotiations with the vendors.

One other important aspect of procuring the IP from an external vendor is the assessment of views and models delivered by the vendor, which will be used with the existing ASIC semi-custom/full custom design flow.

There have been efforts by bodies like IP-XACT to standardize the IP. However, due to various EDA flows and tool choices due to historical reasons etc., an IP delivered by multiple IP vendors may not look the same. It might require generation of some auxiliary views like IBIS views for IOs from spice, milkyway databases, and characterization at custom corners for analysis etc., which might not be available from an IP vendor as a default delivery option.

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