Global Sources
EE Times-Asia
Stay in touch with EE Times Asia
?
EE Times-Asia > Amplifiers/Converters
?
?
Amplifiers/Converters??

Assessing audio DAC jitter sensitivity

Posted: 18 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:clock jitter? time interval error? digital-to-analogue converters?

This application note explains how sampling clock jitter (time interval error or "TIE jitter") affects the performance of delta-sigma digital-to-analogue converters (DACs). New insights explain the importance of separately specifying low-frequency ( 2x passband frequency) jitter tolerance in these devices. The article also provides an application example of a simple highly jittered cycle-skipped sampling clock and describes a method for generating a proper broadband jittered clock. The document then goes on to compare Maxim's audio DAC jitter tolerance to competitor audio DACs. Maxim's high jitter tolerance allows sample clock implementations.

View the PDF document for more information.

Originally published by Maxim Integrated Products Inc. at www.maximintegrated.com as "Analyzing Audio DAC Jitter Sensitivity".





Article Comments - Assessing audio DAC jitter sensitivi...
Comments:??
*? You can enter [0] more charecters.
*Verify code:
?
?
Webinars

Seminars

Visit Asia Webinars to learn about the latest in technology and get practical design tips.

?
?
Back to Top