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JTAG translator allows PCB testing using IP cores

Posted: 19 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:JTAG? PCB testing? IP cores?

JTAG Technologies has announced its CoreCommander for FPGAs that presents a generic solution based on VHDL code that allows engineers to bridge from the standard JTAG test and programming port to proprietary IP cores (e.g. DDR controllers, E-net MAC, USB controllers etc.) and harness them for test purposes. As a member of the company's Embedded Test and Programming (ETP) line, CoreCommander FPGA is targeted at hardware design and test engineers, said the firm.

The base of CoreCommander for FPGAs uses a translator block to access proprietary IP cores through commonly implemented bus structures such as 'Wishbone', AMBA, Avalon and CoreConnect. This translator block, provided as a VHDL module, can be either permanently or temporarily programmed into a gate-array. Linker software provided with the module automatically links the translator block with IP blocks to build the complete (test) design to be programmed in the FPGA.

Use of CoreCommander functions can be either interactive or 'automatic'via library routines in a scripting environment. The interactive mode is intended for use by design engineers to interrogate and control the IP blocks in their FPGA during debug. The automatic mode however is more likely to find favour during (at-speed) logic cluster testing in manufacturing.

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