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Magnachip qualifies Sidense's memory macros for HV process

Posted: 28 Mar 2013 ?? ?Print Version ?Bookmark and Share

Keywords:CMOS? SLP memory macro? 1T-OTP?

Sidense's SLP 1T-OTP macros have been fully qualified for MagnaChip's 180nm 1.8/3.3/18V high-voltage CMOS and mixed-signal process, the companies have announced. According to the firms, semiconductor devices developed in these processes are used in applications such as LED lighting controllers, display controllers and power-management ICs (PMICs) for mobile and other high-volume applications.

"By offering our very dense and low-power SLP memory macros in MagnaChip's HV process, customers have a proven platform in which they can take full advantage of the benefits of 1T-OTP memory and its cost-effectiveness, reliability and security advantages over eFuse, mask ROM and other NVM technologies," stated Tom Schild, Sidense's VP of worldwide sales and marketing.

"By using MagnaChip's specialised process technology with Sidense's reliable and cost-effective non-volatile memory macros, customers can bring to market products that offer distinct advantages over those of their competitors having flexible analogue trimming and/or control program storage," noted Namkyu Park, SVP of marketing at MagnaChip.

SLP macros are available in a comprehensive range of off-the-shelf configurations ranging from 128bits for trim and configuration applications up to 256Kb per macro for code storage and multiple NVM uses. Benefits of Sidense's SLP OTP include small footprints to minimise cost, low power consumption, field-programmability, available configurations with word widths up to 128bits and fast read access to allow executing code from OTP for many applications.

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