Designing safer, more compact computer chips

A team of researchers from the A*STAR Institute of Microelectronics has developed what they say is a powerful modelling method that allows large-scale simulations and optimisation of the fabrication process geared for miniaturizing electronic devices. According to them, the reason behind this is that greater numbers of ever-smaller components are required to fit on computer chips to meet the ongoing demands of miniaturizing electronic devices.

Consequently, computer chips are becoming increasingly crowded. Designers of electronic architectures have therefore followed the lead of urban planners and started to build upward. In so-called '3D packages', for example, several flat, 2D chips can be stacked on top of each other using vertical joints. Controlling the properties of these complex structures is no easy task, as many factors come into play during production, noted Faxing Che, Hongyu Li and co-workers from the A*STAR IME.

Among the challenges of producing tightly packed computer chips is the need to prevent warpage of the underlying silicon wafer as electronics components are stacked on it. Warpage leads to a number of unwanted effects. "Strong warpage can cause wafer breakage, it makes tight packing more difficult and some processing machines cannot handle high-warpage wafers," said Li. The degree of warpage depends on many design and process parameters, and optimising the procedure experimentally is time-consuming and costly.

Using their computer model, Che and Li studied a wide range of parameters that influence the warpage of an 8in diameter silicon wafer. They focused, in particular, on how a silicon substrate responds to the deposition of layers of copper—through which electrical currents eventually flow. "This is the first time that a model has been ... able to predict warpage [at] the level of the entire wafer," stated Li. Moreover, the stress on the wafer can be determined accurately. The calculated values agreed well with experimental data. Importantly, with the computer simulations, the researchers could explore regimes that cannot be easily studied experimentally, such as how the depth of the connections between layers influences wafer warpage.

The next goal is to simulate even larger wafers with variable connection sizes, indicated Li. "Today, there are two industry standards for 3D packaging applications, 8in and 12in wafers, but the latter are becoming increasingly important," she added. The team's model is applicable to these larger wafers, too, but it requires optimisation. Presently, Che, Li and their co-workers are collecting warpage and stress data for 12in wafers. They will use these data for developing their model further, according to Li.