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Designers will jump hurdles to succeed at 14nm node

Posted: 02 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:transistor leakage? EUV? lithography?

Semiconductor scaling used to result in both smaller and faster chips, since clock speed and supply voltage used to be directly- and inversely-proportional to device sizes, respectively. Unfortunately, for the last few generations of process technology, clock speed and supply voltage have changed very little, due to circuit and physical design constraints caused by atomic-scale problems, such as transistor leakage caused by ultra-thin gate oxides.

Many stop-gap measures have been adopted, such as thicker high-k dielectrics. But these have only served to delay addressing the root problems until the 14nm node, according to IBM distinguished engineer, James Warnock, in his paper "Circuit and Physical-Design Challenges at the 14nm Technology Node," presented during the International Symposium on Physical Systems.

"The 14nm node poses a host of challenges for designers, because the solutions to problems with scaling have been postponed by previous generations," said Warnock. "The end is nearish, and will eventually be determined by economic issues, but at 14nm there is no way to get more performance by scaling alone."

The biggest problem with scaling, according to Warnock, has been increased transistor leakage, which designers at previous nodes have mitigated by using steeper sub-threshold slopes and, more recently, by going to high-k dielectrics. In lithography, the lack of commercial extreme ultraviolet (EUV) has been mitigated by double patterning. However, at 14nm neither of these stop-gaps will work, according to Warnock.

"To solve the leakage problem, multi-gate 3D FinFETs have already appeared at 22nm [by Intel] and are quickly being adopted by other chip makers," said Warnock. "FinFETS have inherently steeper threshold slopes and improve random dopant fluctuations [RDFs], but they introduce new sources of variability toosuch as fin width and height."

The 3D aspect ratio of FinFETs compounds other problems, such as line-edge roughening and parasitic capacitance, but also introduces completely new problems. For instance, FinFETs can only have an integer number of 3D fins, presenting designers with choices they have not had to face before, such as how many fins to use.

One solution is the sea-of-fins approach whereby the whole surface of a transistor is studded with dozens of fins, many of which are removed using an etch step. However, new design tools reflecting the new constraints will be needed to aid engineers in picking the number and spacing of fins in multi-gate structures.

New lithographic constraints, such as the need for multi-patterning in 3D, will also require new tools that permit the co-design of FinFET architectures that are compatible with standard libraries. Higher RC delays will also put painful pressures onto automatic routers to identify and optimise wire planes and vias which will not scale to 14nm. New tools will also need to mitigate electro-migration problems as current densities rise in "hot" wires in order to assure that chip lifetimes are not adversely affected at 14nm.

- R. Colin Johnson
??EE Times

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