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I2C bus interface ready for Philips v 3.0 spec

Posted: 05 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:Digital Core Design? I2C? MCU? master? slave?

Polish design house Digital Core Design (DCD) has recently unveiled its latest I2C bus interface soft core. The DI2CMS is fully compatible with Philips v 3.0 specification, allowing it to operate up to 3, 4 Mb/s. The company's latest offering allows master and slave mode, arbitration and clock synchronisation, support for multi-master systems and 7bit and 10bit addressing formats on the I2C, and some other valuable features.

Digital Core Design's family of I2C IP Cores consists of: DI2CM, DI2CS, DI2CSB and the DI2CMS mentioned above. Depending on the target application, they can work as a master, slave, base or master/slave. The DI2CM 每 I2C Bus controller Master 每 performs master communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as the I2C master transmitter and the I2C Master receiver. DI2CS〞I2C Bus controller Slave 每 carries out slave communication between a microprocessor/microcontroller and an I2C Bus. It allows operations as an I2C Slave receiver and an I2C Slave transmitter. And last but not least, the DI2CSB 每 I2C Bus controller Slave/Base version 每 performs communication between an I2C Bus and passive devices, like LCD drivers, memories etc.

Datasheet for the DI2CMS is available here.





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