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Globalfoundries delays 3D IC stack production

Posted: 04 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:through silicon vias? 3D IC stacks? chip designs? silicon interposer? WideIO?

We may not see 3D chip stacks for next-gen smartphones until 2015 or later. We can, however, expect new chip designs for tablets using the much simpler 2.5D stacking techniques by late next year.

The good and bad news comes as Globalfoundries Inc. announced its first functional wafers with through silicon vias (TSVs) using the 20nm process at its Fab 8 in New York. TSVs form the connections between chips in a 3D stack, and Globalfoundries hopes to be an early implementer of the technology.

A year ago, Globalfoundries announced it was installing equipment at Fab 8 worth "tens of millions" in hopes of shipping 28- and 20nm 3D chip stacks in 2014. Now, it says it only expects to use the 20nm process for 3D chips that may not ship in volume until 2015 or later.

However, the foundry does appear to be accelerating work in 65nm at its Singapore Fab 7 on 2.5D stacks that put chips side-by-side on a silicon interposer for a range of uses.

Uses of 2.5D and 3D stacks

Globalfoundries sees three uses for 2.5D stacks and just one for 3D using TSVs.

The 28nm work got a double whammy in recent months when both Texas Instruments and STMicroelectronics quietly cancelled projects for chip stacks using a first-generation Wide IO memory from Jedec, running at 12.8 Gbits/second.

Other mobile SoC makers are said to be adopting Jedec's next-generation WideIO spec that will support data rates up to 25.6 Gb/s and is expected to be finished by the end of the year. They are targeting the 20nm node, in which Globalfoundries conducted its latest tests.

Outlook on costs and yields
The road to chip stacks is still fraught with difficulties, especially for packaging houses. When looking at costs and yields of 3D chip stacks, "my biggest concern is the supply chain by far," said David McCann, vice president of packaging R&D at Globalfoundries.

Most foundries plan to ship wafers with TSVs to packaging companies such as Amkor, ASE and others. The packagers will bond a silicon or glass carrier wafer to the active wafer, thin the active wafer to expose the TSVs then remove the carrier wafer. "That process is slow, tools are expensive and yields are erratic," said McCann.

"The yield of the bonding and especially the de-bonding is very, very poor and I haven't heard a solution for it yet," said Herb Reiter, president of EDA2ASIC Consulting Inc.

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