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Enabling superior FinFET predictability

Posted: 10 Apr 2013 ?? ?Print Version ?Bookmark and Share

Keywords:FinFET? simulation? EDA?

Semiconductor technology has reached crucial technology crossroads; one were the usually-dependable "Moore's Law" provides scant guidance. Scaling continues to charge forward, with 20nm device production expected this year and 14nm device production anticipated sometime in 2014. As the industry fast approaches the 10nm, some real basic choices have to be made. Those choices go to the very basics of semiconductor design and manufacturing and, scarily, those choices need be addressed immediately. In other words, the future is now.

Here's what's happening. On one hand, both fully depleted Silicon on Insulator (SOI) and multi-gate MOSFETs have demonstrated superior electrostatic integrity, tolerance to low channel doping and are considered competing successors to today's classic process technologies. At the same time 22nm, 20nm and 14nm FinFET technologies appear to be the processes du jour for leading semiconductor device and foundry companies. Clearly some critical decisions will have to be made and made soon.

So where to start? One obvious observation is that device analysis and simulation should play an important task in sorting through short term and longer term options. But questions raised by the R&D community challenge the assumption that simulation technology is up to the task.

Simulation's important role
No doubt, device simulation, analysis and optimisation must play an important role. But significantly, more sophisticated methodologies must be built into current approaches, particularly when it comes to providing predictive simulations for 3D transistor structures.

Today, drift diffusion is the most commonly used simulation approach in commercial EDA tools. While it has proven highly effective in meeting most of today's design challenges, the drift diffusion approach has failed to deliver predictive simulations of contemporary FinFETs with deca-nanometre channel lengths. The primary culprit is non-equilibrium, quasiballistic transport exacerbated by strained materials and channel orientation in the FinFet transistor that enhance transport and drive current. A near term solution to this dilemma appears unlikely, so a number of other simulation approaches are undergoing serious and detailed consideration.

One of the most promising, and so far one of the most practical approaches, is 3D Monte Carlo device simulation. In fact, 3D Monte Carlo simulation might prove to be both a short term and long term superior alternative. Monte Carlo device simulations have proven capable of resolving both non-equilibrium transport effects and the impact of orientation and strain on the band structure transport parameters and device performance. As a result, 3D Monte Carlo simulation has proven a fully reliable means to investigate device behaviour early in the design stage.

So why hasn't 3D Monte Carlo simulation found a home in contemporary EDA design practices? The answer lies in the fact that complexity and the computational cost of the 3D Monte Carlo have proven somewhat of a downside which until now has limited its widespread utilisation. However, as the research that follows shows, it is becoming increasingly more obvious that the relentless march of scaling is trumping costs concerns and that 3D Monte Carlo simulation should soon be finding its way into more and more commercial application.

Study parameters
For this research, the Drift Diffusion approach was implemented using a 3D quantum corrected simulations performed with the Drift Diffusion module incorporated in the Gold Standard Simulations' (GSS) GARAND physical simulation tool using a standard silicon mobility model. GARAND is a statistical 3D 'atomistic' simulator that specialises in simulation of statistical variability and reliability in current and future CMOS transistors. GARAND interfaces to both a common GSS database and the GSS cluster simulation engine.

The simulator's 3D Monte Carlo module employs self-consistent quantum corrections based on the density gradient (DG) approximation using the corresponding DG quantum potential as a driving force for the electrons. Non-parabolic approximation to the silicon conduction was adopted for the simulation of the electron transport in the reported n-channel FinFETs. The standard f-type and g-type phonon model was calibrated to experimental bulk velocity-field data.

The simulations of the ID-VG transistor characteristics were carried out at VDD=0.05V and VDD=VDS=0.90V for each of the five devices. Variability sources were introduced automatically through command lines of the GARAND input language. GARAND's visualisation modules are based on Paraview and include graphing, statistical and 3D modules.

The GARAND tool was used in this research because it is the only commercial physical simulation tool that provides both a Drift Diffusion approach and 3D Monte Carlo approach. It is also the only commercial tool that offers a 'true' 3D ensemble Monte Carlo simulation module that has consistently demonstrated accurate quantum corrections.

The simulated devices are based on an initial 20nm gate length SOI FinFET. The fin width and fin height are 10nm and 25nm respectively. The equivalent oxide thickness of the high-k/metal gate stack is 0.8-nanomeners (nm). The top of the conducting fin is insulated from the gate by a thicker layer of silicon nitride. The channel length of this initial transistor was scaled further to 19nm, 18nm, 17nm and 16nm. No other design parameters were altered during the physical gate length scaling.

The simulation was conducted at the worst temperature corner of 358K since these devices were designed for SRAM applications.

Drift diffusion and 3D Monte Carlo comparisons
Better predictive results were delivered through a 3D Monte Carlo approach, as demonstrated in figure 1. This figure shows a comparison of a typical electron equiconcentration surface through the fin obtained from Drift Diffusion and Monte Carlo simulations at VDD=0.90V and VDS=0.90V. The two conducting channels are clearly visible.

Figure 1: Typical electron equi-concentration surface through a device fin from quantum corrected DD (top) and MC (bottom) simulation. The self-consistent potential together with potential contours are overlaid on the surface.

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